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Code Activity
17495 commits 134 branches 69 tags 58 MiB
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2607 commits

Author SHA1 Message Date
Johan Olby
267faa0deb
Merge 4d215665a1 into d4f39588a7 2026-07-14 22:08:17 +03:00
Emil J. Tywoniak
eb96123030 dfflibmap: add regression test for resetval clobber 2026-07-14 18:02:02 +02:00
Johan Olby
4d215665a1
gowin: infer DSP multiply-accumulate for the GW5A family 
Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.

The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).

alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
 2026-07-13 20:57:08 +02:00
nella
dddf137888
Merge pull request #6024 from YosysHQ/nella/scl-build-date 
Include build datetime in scl cache hash
 2026-07-13 11:54:45 +00:00
nella
ede98b81ac
Merge pull request #6023 from b-michi/michaelbaier/sc-649/segmentation-fault-during-proc-init-with 
Michaelbaier/sc 649/segmentation fault during proc init with
 2026-07-10 13:07:58 +00:00
nella
eb93f5a066 Add scl caching test. 2026-07-10 14:52:06 +02:00
Michael Baier
dca9234d86 Testcases for new truncation checks 2026-07-10 14:37:19 +02:00
Miodrag Milanovic
f2f3f31646 Add initial codecov support 2026-07-10 12:19:59 +02:00
Michael Baier
086c50763d Tescases for Width Limit, Resize and Overflow 2026-07-09 14:34:56 +02:00
Michael Baier
3adb423e9e Added Testcase for bug1206 2026-07-09 14:34:56 +02:00
Lofty
75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
nella
8dc32cbf4e
Merge pull request #6012 from YosysHQ/nella/fix-opt-reduce 
`opt_reduce`: restore pmux b-slice == a elim
 2026-07-08 13:36:04 +00:00
nella
f6d810acf9 Restore pmux elim. 2026-07-08 11:58:30 +02:00
nella
f5809a7c2c
Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
Miodrag Milanovic
8ad4ffcdd1 Cleanup 2026-07-08 08:34:01 +02:00
nella
8a2499b544
Merge pull request #5986 from YosysHQ/nella/x-wildcard 
fix case item containing x/z treated as wildcard in proc_rmdead
 2026-07-07 08:00:02 +00:00
Lofty
4e30b5c47b
Merge pull request #5997 from mole99/leo/fabulous-updates 
FABulous Updates
 2026-07-07 06:35:32 +00:00
nella
310016a812 Rm. 2026-07-07 04:03:17 +02:00
nella
006cbc8f72
Merge pull request #5842 from YosysHQ/nella/opt_dff_elim_improvements 
opt_dff: Eliminate equivalent bits
 2026-07-06 12:02:50 +00:00
nella
0e56ca02ed Make opt_dff -sat conflict with -keepdc. 2026-07-06 13:47:10 +02:00
nella
2b4ec9d57a Fix covers_nothing. 2026-07-06 13:26:00 +02:00
Leo Moser
e87d8e162e fabulous: update tests for new options 
Signed-off-by: Leo Moser <leomoser99@gmail.com>
 2026-07-01 13:38:44 +02:00
Leo Moser
655cb40d0f fabulous: add --cells-map option 
Signed-off-by: Leo Moser <leomoser99@gmail.com>
 2026-06-30 16:09:51 +02:00
nella
6a45e7b290 Add tests. 2026-06-25 11:14:54 +02:00
nella
6675c45e29 Fix (async latch). 2026-06-24 13:01:52 +02:00
nella
a800a5b5cb Fix. 2026-06-24 12:13:55 +02:00
nella
a8b4715298 Fix. 2026-06-24 11:48:20 +02:00
nella
1186e5af61 Fix. 2026-06-24 11:11:19 +02:00
nella
a3b8609c84 Add -nolatches check option. 2026-06-24 10:38:10 +02:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Miodrag Milanovic
3ac58b3ac1 Fixed line endings 2026-06-23 07:17:22 +02:00
Miodrag Milanovic
1f0ac8fffc Remove utf-8 marker 2026-06-23 07:14:20 +02:00
Miodrag Milanovic
f362e1db0e Remove executable flag from .v files 2026-06-23 07:12:43 +02:00
KrystalDelusion
e20a9168fb
Merge pull request #5971 from YosysHQ/krys/upto_indexing 
write_verilog: Fix upto indexing for single bit
 2026-06-22 23:04:16 +00:00
nella
57ec784983
Merge pull request #5953 from YosysHQ/nella/muxcover-enhancements 
Add muxcover x peepopt regression test (#964).
 2026-06-22 10:13:43 +00:00
nella
8f5d2d5894 Use -assert-none. 2026-06-22 11:12:00 +02:00
nella
3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index 
Optimize upto vector indexing (Fix #892).
 2026-06-22 09:05:26 +00:00
nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup 
Add warnings and errors to `sim -r` with VCD code path
 2026-06-22 09:02:32 +00:00
Lofty
091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
Krystine Sherwin
b77bb851ed
tests: Add mixed_upto write_verilog test 2026-06-19 11:20:01 +12:00
nella
5d7486115a
Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 
Fix: `read_verilog` doesn't respect `signed` keyword
 2026-06-18 16:53:37 +00:00
nella
2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer 
proc_dlatch - infer $adlatch (Fix #5910).
 2026-06-18 16:50:48 +00:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745 
Fix  `chparam` values are unsigned when using read_verilog frontend
 2026-06-18 16:50:22 +00:00
nella
b3b1394cf1 Fixup level policy. 2026-06-18 18:00:51 +02:00
nella
32a268d745 Emit errors before dfflegalize. 2026-06-18 17:07:24 +02:00
nella
b2d688dbf9 Error out on latches. 2026-06-17 17:36:32 +02:00
nella
c814ef35e3 Emit latch warning. 2026-06-17 11:27:43 +02:00
Miodrag Milanović
e2903c4a5c
Merge pull request #5959 from YosysHQ/improve_test 
Improve test
 2026-06-16 08:46:11 +00:00
nella
c0709b1b4e Fixup issue test. 2026-06-15 16:23:44 +02:00