Emit errors before dfflegalize.

tests/various/check_nolatches.ys

@@ -29,3 +29,19 @@ EOT
 proc
 logger -expect error "Found 1 problems in" 1
 check -nolatches -assert
+
+design -reset
+
+read_verilog <<EOT
+module top(input g, d, output reg q, output y);
+always @* if (g) q = d;
+wire u;
+assign y = u;
+endmodule
+EOT
+proc
+scratchpad -set check.latchonly 1
+logger -expect warning "is a latch of type" 1
+logger -expect warning "used but has no driver" 0
+logger -expect error "Found 1 problems in" 1
+check -assert

tests/various/synth_latch_warning.ys

@@ -15,5 +15,6 @@ synth_ice40 -latches auto
 select -assert-count 1 t:SB_LUT4
 
 design -load read
-logger -expect error "selection is not empty: t:._DLATCH_" 1
+logger -expect warning "Latch inferred for signal" 1
+logger -expect error "Found 1 problems in 'check -assert'" 1
 synth_ice40