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Tescases for Width Limit, Resize and Overflow

This commit is contained in:
Michael Baier 2026-07-09 11:58:07 +02:00
parent eb4e29810e
commit 086c50763d
4 changed files with 40 additions and 0 deletions

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@ -0,0 +1,6 @@
logger -expect error "Memory width .* out of range" 1
read_rtlil <<EOT
module \foo
memory width 1073741824 \mem
end
EOT

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@ -0,0 +1,6 @@
logger -expect error "Memory width .* out of range" 1
read_rtlil <<EOT
module \foo
memory width 4294967396 \mem
end
EOT

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@ -0,0 +1,6 @@
logger -expect error "Wire width .* out of range" 1
read_rtlil <<EOT
module \foo
wire width 4294967396 \bar
end
EOT

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@ -284,6 +284,28 @@ namespace RTLIL {
EXPECT_EQ(c, Const(0xe, 4));
}
TEST_F(KernelRtlilTest, ConstResizeWidthLimit) {
Const c;
EXPECT_DEATH(c.resize(RTLIL::WIDTH_LIMIT, Sx), "");
EXPECT_NO_FATAL_FAILURE(c.resize(RTLIL::WIDTH_LIMIT - 1, Sx));
}
TEST_F(KernelRtlilTest, ConstFromLongLongWidthLimit) {
EXPECT_DEATH(Const(0, RTLIL::WIDTH_LIMIT), "");
EXPECT_NO_FATAL_FAILURE(Const(0, RTLIL::WIDTH_LIMIT - 1));
}
TEST_F(KernelRtlilTest, ConstFromStateWidthLimit) {
EXPECT_DEATH(Const(Sx, RTLIL::WIDTH_LIMIT), "");
EXPECT_NO_FATAL_FAILURE(Const(Sx, RTLIL::WIDTH_LIMIT - 1));
}
TEST_F(KernelRtlilTest, ModuleAddWireWidthLimit) {
std::unique_ptr<Module> mod = std::make_unique<Module>();
EXPECT_DEATH(mod->addWire(ID(test), RTLIL::WIDTH_LIMIT), "");
EXPECT_NO_FATAL_FAILURE(mod->addWire(ID(test), RTLIL::WIDTH_LIMIT - 1));
}
TEST_F(KernelRtlilTest, ConstEqualStr) {
EXPECT_EQ(Const("abc"), Const("abc"));
EXPECT_NE(Const("abc"), Const("def"));