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Fixup level policy.

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This commit is contained in:
nella 2026-06-18 18:00:51 +02:00
parent 32a268d745
commit b3b1394cf1
15 changed files with 55 additions and 55 deletions
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12
passes/proc/proc_dlatch.cc
View file

@ -346,7 +346,7 @@ struct proc_dlatch_db_t
};
enum LatchPolicy {
POLICY_AUTO,
POLICY_INFO,
POLICY_WARN,
POLICY_ERROR
};
@ -475,9 +475,9 @@ struct ProcDlatchPass : public Pass {
log("This pass identifies latches in the processes and converts them to\n");
log("d-type latches.\n");
log("\n");
log(" -latches <auto|warn|error>\n");
log(" -latches <info|warn|error>\n");
log(" controls how the inference of a latch is reported. Alternatively, one\n");
log(" can use the 'proc.latches' scratchpad variable.\n");
log(" can use the 'proc.latches' scratchpad variable. Defaults to 'warn'.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -500,14 +500,14 @@ struct ProcDlatchPass : public Pass {
policy_str = design->scratchpad_get_string("proc.latches", "warn");
LatchPolicy policy;
if (policy_str == "auto")
policy = POLICY_AUTO;
if (policy_str == "info")
policy = POLICY_INFO;
else if (policy_str == "warn")
policy = POLICY_WARN;
else if (policy_str == "error")
policy = POLICY_ERROR;
else
log_cmd_error("Invalid value '%s' for -latches (expected auto|warn|error).\n", policy_str.c_str());
log_cmd_error("Invalid value '%s' for -latches (expected info|warn|error).\n", policy_str.c_str());
for (auto mod : design->all_selected_modules()) {
proc_dlatch_db_t db(mod);

10
techlibs/efinix/synth_efinix.cc
View file

@ -63,11 +63,11 @@ struct SynthEfinixPass : public ScriptPass
log(" -nobram\n");
log(" do not use EFX_RAM_5K cells in output netlist\n");
log("\n");
log(" -latches <auto|warn|error>\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'auto' permits them without complaint.\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -139,8 +139,8 @@ struct SynthEfinixPass : public ScriptPass
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (latches != "auto" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected auto, warn or error)\n", latches.c_str());
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
log_header(design, "Executing SYNTH_EFINIX pass.\n");
log_push();
@ -160,7 +160,7 @@ struct SynthEfinixPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
run("check");
run("flatten");
run("tribuf -logic");

10
techlibs/fabulous/synth_fabulous.cc
View file

@ -116,11 +116,11 @@ struct SynthPass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n");
log("\n");
log(" -latches <auto|warn|error>\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'auto' permits them without complaint.\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -260,8 +260,8 @@ struct SynthPass : public ScriptPass
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (latches != "auto" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected auto, warn or error)\n", latches.c_str());
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
log_header(design, "Executing SYNTH_FABULOUS pass.\n");
log_push();
@ -292,7 +292,7 @@ struct SynthPass : public ScriptPass
run("hierarchy -check");
} else
run(stringf("hierarchy -check -top %s", top_module));
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
}

10
techlibs/ice40/synth_ice40.cc
View file

@ -117,11 +117,11 @@ struct SynthIce40Pass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n");
log("\n");
log(" -latches <auto|warn|error>\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'auto' permits them without complaint.\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -277,8 +277,8 @@ struct SynthIce40Pass : public ScriptPass
log_cmd_error("This command only operates on fully selected designs!\n");
if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
log_cmd_error("Invalid or no device specified: '%s'\n", device_opt);
if (latches != "auto" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected auto, warn or error)\n", latches.c_str());
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n");
@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
{
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
}
if (check_label("flatten", "(unless -noflatten)"))

10
techlibs/lattice/synth_lattice.cc
View file

@ -156,11 +156,11 @@ struct SynthLatticePass : public ScriptPass
log(" implement constant comparisons in soft logic, do not involve\n");
log(" hard carry chains\n");
log("\n");
log(" -latches <auto|warn|error>\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'auto' permits them without complaint.\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" (ignored with -asyncprld, which has a latch primitive)\n");
log("\n");
log("\n");
@ -337,8 +337,8 @@ struct SynthLatticePass : public ScriptPass
if (family.empty())
log_cmd_error("Lattice family parameter must be set.\n");
if (latches != "auto" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected auto, warn or error)\n", latches.c_str());
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (family == "ecp5") {
postfix = "_ecp5";
@ -416,7 +416,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + ((asyncprld || latches == "auto") ? std::string("auto") : std::string("warn")));
run("proc -latches " + ((asyncprld || latches == "info") ? std::string("info") : std::string("warn")));
if (flatten || help_mode) {
run("check");
run("flatten");

10
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -97,11 +97,11 @@ struct SynthNanoXplorePass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n");
log("\n");
log(" -latches <auto|warn|error>\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'auto' permits them without complaint.\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -217,8 +217,8 @@ struct SynthNanoXplorePass : public ScriptPass
}
extra_args(args, argidx, design);
if (latches != "auto" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected auto, warn or error)\n", latches.c_str());
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (family.empty()) {
//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
@ -263,7 +263,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + (latches == "auto" ? std::string("auto") : std::string("warn")));
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");

10
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -72,11 +72,11 @@ struct SynthQuickLogicPass : public ScriptPass {
log(" use old ABC flow, which has generally worse mapping results but is less\n");
log(" likely to have bugs.\n");
log("\n");
log(" -latches <auto|warn|error>\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'auto' permits them without complaint.\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" (only applies to the pp3 family)\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -190,8 +190,8 @@ struct SynthQuickLogicPass : public ScriptPass {
if (family != "pp3" && family != "qlf_k6n10f")
log_cmd_error("Invalid family specified: '%s'\n", family);
if (latches != "auto" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected auto, warn or error)\n", latches.c_str());
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
@ -226,7 +226,7 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("prepare")) {
run("proc -latches " + ((family == "pp3" && latches != "auto") ? std::string("warn") : std::string("auto")));
run("proc -latches " + ((family == "pp3" && latches != "info") ? std::string("warn") : std::string("info")));
if (flatten) {
run("check");
run("flatten", "(unless -noflatten)");

6
tests/arch/ecp5/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -latches auto
synth_ecp5 -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -latches auto
synth_ecp5 -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -latches auto
synth_ecp5 -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
select -assert-count 1 t:PFUMX

2
tests/arch/ecp5/latches_abc9.ys
View file

@ -8,6 +8,6 @@ assign q = ~l;
endmodule
EOT
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -abc9 -latches auto
synth_ecp5 -abc9 -latches info
select -assert-count 2 t:LUT4
select -assert-none t:LUT4 %% t:* %D

6
tests/arch/efinix/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix -latches auto
synth_efinix -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix -latches auto
synth_efinix -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix -latches auto
synth_efinix -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4

6
tests/arch/ice40/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 -latches auto
synth_ice40 -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 -latches auto
synth_ice40 -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 -latches auto
synth_ice40 -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4

6
tests/arch/nanoxplore/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad -latches auto
synth_nanoxplore -noiopad -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_LUT
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad -latches auto
synth_nanoxplore -noiopad -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_LUT
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad -latches auto
synth_nanoxplore -noiopad -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:NX_LUT

6
tests/arch/quicklogic/pp3/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -latches auto
synth_quicklogic -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
@ -17,7 +17,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -latches auto
synth_quicklogic -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
@ -30,7 +30,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -latches auto
synth_quicklogic -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4

4
tests/proc/proc_latches.ys
View file

@ -10,14 +10,14 @@ logger -check-expected
design -reset
# auto
# info
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect-no-warnings
proc -latches auto
proc -latches info
logger -check-expected
design -reset

2
tests/various/synth_latch_warning.ys
View file

@ -11,7 +11,7 @@ logger -check-expected
select -assert-count 1 t:SB_LUT4
design -load read
synth_ice40 -latches auto
synth_ice40 -latches info
select -assert-count 1 t:SB_LUT4
design -load read