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Fixup level policy.

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This commit is contained in:
nella 2026-06-18 18:00:51 +02:00
parent 32a268d745
commit b3b1394cf1
15 changed files with 55 additions and 55 deletions
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6
tests/arch/ecp5/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -latches auto
synth_ecp5 -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -latches auto
synth_ecp5 -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -latches auto
synth_ecp5 -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
select -assert-count 1 t:PFUMX

2
tests/arch/ecp5/latches_abc9.ys
View file

@ -8,6 +8,6 @@ assign q = ~l;
endmodule
EOT
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -abc9 -latches auto
synth_ecp5 -abc9 -latches info
select -assert-count 2 t:LUT4
select -assert-none t:LUT4 %% t:* %D

6
tests/arch/efinix/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix -latches auto
synth_efinix -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix -latches auto
synth_efinix -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix -latches auto
synth_efinix -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4

6
tests/arch/ice40/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 -latches auto
synth_ice40 -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 -latches auto
synth_ice40 -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 -latches auto
synth_ice40 -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4

6
tests/arch/nanoxplore/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad -latches auto
synth_nanoxplore -noiopad -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_LUT
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad -latches auto
synth_nanoxplore -noiopad -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_LUT
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad -latches auto
synth_nanoxplore -noiopad -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:NX_LUT

6
tests/arch/quicklogic/pp3/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -latches auto
synth_quicklogic -latches info
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
@ -17,7 +17,7 @@ design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -latches auto
synth_quicklogic -latches info
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
@ -30,7 +30,7 @@ design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic -latches auto
synth_quicklogic -latches info
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4

4
tests/proc/proc_latches.ys
View file

@ -10,14 +10,14 @@ logger -check-expected
design -reset
# auto
# info
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect-no-warnings
proc -latches auto
proc -latches info
logger -check-expected
design -reset

2
tests/various/synth_latch_warning.ys
View file

@ -11,7 +11,7 @@ logger -check-expected
select -assert-count 1 t:SB_LUT4
design -load read
synth_ice40 -latches auto
synth_ice40 -latches info
select -assert-count 1 t:SB_LUT4
design -load read