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nella 2026-07-07 04:03:17 +02:00
parent 2b4ec9d57a
commit 310016a812
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tests/verilog/temp/issue4402_syn.v
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/* Generated by Yosys 0.66+154 (git sha1 23aadd92a-dirty, Release, Clang /nix/store/mw4gasdvwgscgpxpzihjgchfhs3hhqhn-clang-wrapper-21.1.8/bin/clang++ 21.1.8) [git@github.com:YosysHQ/yosys at nella/x-wildcard] */
(* top = 1 *)
(* src = "<<EOT:1.1-12.10" *)
module top(y, clk, wire0);
(* src = "<<EOT:2.15-2.16" *)
output y;
wire y;
(* src = "<<EOT:3.14-3.17" *)
input clk;
wire clk;
(* src = "<<EOT:4.21-4.26" *)
input signed wire0;
wire signed wire0;
(* src = "<<EOT:9.3-11.6" *)
wire _0_;
(* src = "<<EOT:6.7-6.15" *)
wire _1_;
(* src = "<<EOT:7.7-7.15" *)
wire _2_;
(* src = "<<EOT:10.21-10.31" *)
wire _3_;
(* src = "<<EOT:10.45-10.50" *)
wire _4_;
(* src = "<<EOT:10.55-10.70" *)
wire _5_;
(* src = "<<EOT:10.13-10.71" *)
wire _6_;
(* src = "<<EOT:5.7-5.11" *)
reg reg1;
(* src = "<<EOT:6.7-6.11" *)
wire var2;
(* src = "<<EOT:7.7-7.11" *)
wire var3;
assign _3_ = $signed(wire0) <= (* src = "<<EOT:10.21-10.31" *) $signed(32'd0);
(* src = "<<EOT:9.3-11.6" *)
always @(posedge clk)
reg1 <= _6_;
assign _6_ = _3_ ? (* src = "<<EOT:10.13-10.71" *) 1'h0 : 1'h1;
assign y = reg1;
assign _2_ = 1'h0;
assign _1_ = 1'h0;
assign _0_ = _6_;
assign var3 = 1'h0;
assign var2 = 1'h0;
assign _4_ = var3;
assign _5_ = 1'h1;
endmodule