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Add -nolatches check option.

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This commit is contained in:
nella 2026-06-24 10:38:10 +02:00
parent b3b1394cf1
commit a3b8609c84
8 changed files with 28 additions and 40 deletions
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11
passes/cmds/check.cc
View file

@ -65,6 +65,10 @@ struct CheckPass : public Pass {
log(" $_DLATCH_*/$_DLATCHSR_* mappings) remaining in the design. Use this\n");
log(" before techmapping in flows that must not emit latches.\n");
log("\n");
log(" -latchonly\n");
log(" check only for latch cells (as listed under -nolatches), skipping all\n");
log(" other checks.\n");
log("\n");
log(" -allow-tbuf\n");
log(" modify the -mapped behavior to still allow $_TBUF_ cells\n");
log("\n");
@ -85,6 +89,7 @@ struct CheckPass : public Pass {
bool initdrv = false;
bool mapped = false;
bool nolatches = false;
bool latchonly = false;
bool allow_tbuf = false;
bool assert_mode = false;
bool force_detailed_loop_check = false;
@ -108,6 +113,10 @@ struct CheckPass : public Pass {
nolatches = true;
continue;
}
if (args[argidx] == "-latchonly") {
latchonly = true;
continue;
}
if (args[argidx] == "-allow-tbuf") {
allow_tbuf = true;
continue;
@ -124,8 +133,6 @@ struct CheckPass : public Pass {
}
extra_args(args, argidx, design);
bool latchonly = design->scratchpad_get_bool("check.latchonly", false);
log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
for (auto module : design->selected_whole_modules_warn())

9
techlibs/efinix/synth_efinix.cc
View file

@ -204,12 +204,9 @@ struct SynthEfinixPass : public ScriptPass
{
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
if (help_mode)
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -D NO_LUT -map +/efinix/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");

9
techlibs/fabulous/synth_fabulous.cc
View file

@ -373,12 +373,9 @@ struct SynthPass : public ScriptPass
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
}
if (help_mode)
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v");
if (help_mode) {

9
techlibs/ice40/synth_ice40.cc
View file

@ -420,12 +420,9 @@ struct SynthIce40Pass : public ScriptPass
run("ice40_opt", "(only if -abc2)");
}
if (help_mode)
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/ice40/latches_map.v");
if (noabc || flowmap || help_mode) {
run("simplemap", " (if -noabc or -flowmap)");

9
techlibs/lattice/synth_lattice.cc
View file

@ -548,12 +548,9 @@ struct SynthLatticePass : public ScriptPass
run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) {
if (help_mode)
run("check -assert", "(skip if -asyncprld; only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
}

9
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -340,12 +340,9 @@ struct SynthNanoXplorePass : public ScriptPass
run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
run("opt_merge");
if (help_mode)
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map +/nanoxplore/latches_map.v");
run("techmap -map +/nanoxplore/cells_map.v");
run("opt_expr -undriven -mux_undef");

9
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -331,12 +331,9 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
if (help_mode)
run("check -assert", "(only if -latches error, the default)");
else if (latches == "error") {
active_design->scratchpad_set_bool("check.latchonly", true);
run("check -assert");
active_design->scratchpad_unset("check.latchonly");
}
run("check -latchonly -assert", "(only if -latches error, the default)");
else if (latches == "error")
run("check -latchonly -assert");
run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");

3
tests/various/check_nolatches.ys
View file

@ -40,8 +40,7 @@ assign y = u;
endmodule
EOT
proc
scratchpad -set check.latchonly 1
logger -expect warning "is a latch of type" 1
logger -expect warning "used but has no driver" 0
logger -expect error "Found 1 problems in" 1
check -assert
check -latchonly -assert