mirror of
https://github.com/YosysHQ/yosys
synced 2026-06-26 10:38:47 +00:00
Remove trailing whitespaces
This commit is contained in:
Miodrag Milanovic
parent
48a3dcc02a
commit
a689342207
317 changed files with 3136 additions and 3136 deletions
|
|
@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
|
|||
parameter WIDTHA = 4;
|
||||
parameter SIZEA = 1024;
|
||||
parameter ADDRWIDTHA = 10;
|
||||
|
||||
|
||||
parameter WIDTHB = 16;
|
||||
parameter SIZEB = 256;
|
||||
parameter ADDRWIDTHB = 8;
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ hierarchy -top block_ram
|
|||
synth_analogdevices -top block_ram -noiopad
|
||||
cd block_ram # Constrain all select calls below inside the top module
|
||||
# select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive.
|
||||
|
||||
|
||||
# Check that distributed memory without parameters is not modified
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
@ -13,7 +13,7 @@ synth_analogdevices -top distributed_ram -noiopad
|
|||
cd distributed_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 8 t:RAMS64X1
|
||||
select -assert-count 8 t:FFRE
|
||||
|
||||
|
||||
# Set ram_style distributed to blockram memory; will be implemented as distributed
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
@ -22,7 +22,7 @@ synth_analogdevices -top block_ram -noiopad
|
|||
cd block_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 64 t:RAMS64X1
|
||||
select -assert-count 4 t:FFRE
|
||||
|
||||
|
||||
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
@ -30,7 +30,7 @@ setattr -set logic_block 1 block_ram/m:*
|
|||
synth_analogdevices -top block_ram -noiopad
|
||||
cd block_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 0 t:RBRAM2
|
||||
|
||||
|
||||
# Set ram_style block to a distributed memory; will be implemented as blockram
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ select -assert-count 1 t:RBRAM2
|
|||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_style "block" m:memory
|
||||
synth_analogdevices -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
|
|
@ -62,7 +62,7 @@ select -assert-count 1 t:RBRAM2
|
|||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_analogdevices -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
|
|
|
|||
|
|
@ -3,14 +3,14 @@ module led_blink (
|
|||
input clk,
|
||||
output ledc
|
||||
);
|
||||
|
||||
|
||||
reg [6:0] led_counter = 0;
|
||||
always @( posedge clk ) begin
|
||||
led_counter <= led_counter + 1;
|
||||
end
|
||||
assign ledc = !led_counter[ 6:3 ];
|
||||
|
||||
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices
|
||||
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ module top(input signed [24:0] A, input signed [17:0] B, output [47:0] P);
|
|||
assign P = A * B;
|
||||
endmodule
|
||||
EOT
|
||||
synth_analogdevices
|
||||
synth_analogdevices
|
||||
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
|
||||
opt -full -fine
|
||||
select -assert-count 2 t:$mul
|
||||
|
|
@ -34,7 +34,7 @@ EOT
|
|||
async2sync
|
||||
techmap -map +/analogdevices/dsp_map.v
|
||||
verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
|
||||
synth_analogdevices
|
||||
synth_analogdevices
|
||||
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
|
||||
opt -full -fine
|
||||
select -assert-count 0 t:* t:$assert %d
|
||||
|
|
|
|||
|
|
@ -233,7 +233,7 @@ endmodule // double_sync_ram_sdp
|
|||
|
||||
|
||||
module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
|
||||
(input wire clk_a, clk_b,
|
||||
(input wire clk_a, clk_b,
|
||||
input wire write_enable_a, write_enable_b,
|
||||
input wire read_enable_a, read_enable_b,
|
||||
input wire [DATA_WIDTH-1:0] write_data_a, write_data_b,
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
state <= #1 IDLE;
|
||||
gnt_0 <= 0;
|
||||
gnt_1 <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
case(state)
|
||||
IDLE : if (req_0 == 1'b1) begin
|
||||
|
|
|
|||
|
|
@ -13,5 +13,5 @@ module top(out, clk, in);
|
|||
begin
|
||||
out <= out >> 1;
|
||||
out[7] <= in;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -3,13 +3,13 @@ module led_blink (
|
|||
input clk,
|
||||
output ledc
|
||||
);
|
||||
|
||||
|
||||
reg [6:0] led_counter = 0;
|
||||
always @( posedge clk ) begin
|
||||
led_counter <= led_counter + 1;
|
||||
end
|
||||
assign ledc = !led_counter[ 6:3 ];
|
||||
|
||||
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
|
|||
|
|
@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v
|
|||
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp
|
||||
hierarchy -top sync_ram_tdp
|
||||
synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp
|
||||
select -assert-count 1 t:DP16KD
|
||||
select -assert-count 1 t:DP16KD
|
||||
select -assert-none t:LUT4
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@ flatten
|
|||
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
|
||||
select -assert-count 8 t:TRELLIS_FF
|
||||
select -assert-none t:TRELLIS_FF %% t:* %D
|
||||
|
|
|
|||
|
|
@ -3,13 +3,13 @@ module led_blink (
|
|||
input clk,
|
||||
output ledc
|
||||
);
|
||||
|
||||
|
||||
reg [6:0] led_counter = 0;
|
||||
always @( posedge clk ) begin
|
||||
led_counter <= led_counter + 1;
|
||||
end
|
||||
assign ledc = !led_counter[ 6:3 ];
|
||||
|
||||
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
|
|||
|
|
@ -182,20 +182,20 @@ module \ahb_async_sram_halfwidth
|
|||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
|
||||
switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
|
||||
case 1'1
|
||||
case
|
||||
case
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
|
||||
switch \ahbls_hready
|
||||
case 1'1
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
|
||||
switch \ahbls_htrans [1]
|
||||
case 1'1
|
||||
case
|
||||
case
|
||||
end
|
||||
case
|
||||
case
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
|
||||
switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
|
||||
case 1'1
|
||||
case
|
||||
case
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ EOT
|
|||
techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
|
||||
|
||||
async2sync
|
||||
equiv_make top ref equiv
|
||||
select -assert-any -module equiv t:$equiv
|
||||
equiv_induct
|
||||
equiv_make top ref equiv
|
||||
select -assert-any -module equiv t:$equiv
|
||||
equiv_induct
|
||||
equiv_status -assert
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ parameter SKIP_RDEN = 1;
|
|||
input clk;
|
||||
input write_enable, read_enable;
|
||||
input [DATA_WIDTH - 1 : 0] write_data;
|
||||
input [ADDR_WIDTH - 1 : 0] addr;
|
||||
input [ADDR_WIDTH - 1 : 0] addr;
|
||||
output [DATA_WIDTH - 1 : 0] read_data;
|
||||
|
||||
(* ram_style = "huge" *)
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
@ -120,7 +120,7 @@ output reg cout;
|
|||
input [n:0] a;
|
||||
input [n:0] b;
|
||||
input [n-1:0] c;
|
||||
always @(*)
|
||||
always @(*)
|
||||
begin
|
||||
{cout,out} = a * b + c;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
@ -27,7 +27,7 @@ output reg [d_width-1:0] q;
|
|||
reg [d_width-1:0] mem [mem_depth-1:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we) begin
|
||||
if (we) begin
|
||||
mem[waddr] <= data;
|
||||
end else begin
|
||||
q <= mem[waddr];
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
@ -28,7 +28,7 @@ reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
|
|||
always @ (posedge clka)
|
||||
begin
|
||||
addra_reg <= addra;
|
||||
|
||||
|
||||
if(wea) begin
|
||||
mem[addra] <= dataina;
|
||||
qa <= dataina;
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
@ -28,7 +28,7 @@ reg [d_width-1:0] mem [mem_depth-1:0];
|
|||
assign q = mem[waddr];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we)
|
||||
if (we)
|
||||
mem[waddr] <= data;
|
||||
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
@ -32,7 +32,7 @@ module uram_sr(clk, wr, raddr, din, waddr, dout);
|
|||
end
|
||||
|
||||
always@(posedge clk) begin
|
||||
raddr_reg <= raddr;
|
||||
raddr_reg <= raddr;
|
||||
if(wr)
|
||||
mem[waddr]<= din;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
# ISC License
|
||||
#
|
||||
#
|
||||
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ always @(posedge clk) begin
|
|||
read_addr <= counter;
|
||||
read_val <= mem[counter];
|
||||
end else begin
|
||||
did_read <= 1'b0;
|
||||
did_read <= 1'b0;
|
||||
end
|
||||
|
||||
if (!done)
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ chparam -set DEPTH_LOG2 5 -set WIDTH 36
|
|||
prep
|
||||
opt_dff
|
||||
prep -rdff
|
||||
synth_nanoxplore
|
||||
synth_nanoxplore
|
||||
clean_zerowidth
|
||||
select -assert-none t:$mem_v2 t:$mem
|
||||
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
|
||||
|
|
@ -18,7 +18,7 @@ chparam -set DEPTH_LOG2 6 -set WIDTH 18
|
|||
prep
|
||||
opt_dff
|
||||
prep -rdff
|
||||
synth_nanoxplore
|
||||
synth_nanoxplore
|
||||
clean_zerowidth
|
||||
select -assert-none t:$mem_v2 t:$mem
|
||||
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
|
||||
|
|
@ -34,7 +34,7 @@ chparam -set DEPTH_LOG2 8 -set WIDTH 18
|
|||
prep
|
||||
opt_dff
|
||||
prep -rdff
|
||||
synth_nanoxplore
|
||||
synth_nanoxplore
|
||||
clean_zerowidth
|
||||
select -assert-none t:$mem_v2 t:$mem
|
||||
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
|
|||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd my_dff # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:sdffsre
|
||||
select -assert-none t:sdffsre %% t:* %D
|
||||
select -assert-none t:sdffsre %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top my_dffe
|
||||
|
|
@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
|
|||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd my_dffe # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:sdffsre
|
||||
select -assert-none t:sdffsre %% t:* %D
|
||||
select -assert-none t:sdffsre %% t:* %D
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ initial begin
|
|||
end
|
||||
|
||||
`MEM_TEST_VECTOR
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
|
|||
always @(posedge clk) begin
|
||||
if (i < VECTORLEN-1) begin
|
||||
if (i > 0) begin
|
||||
if($past(rce_a))
|
||||
if($past(rce_a))
|
||||
assert(rq_a == rq_a_e);
|
||||
if($past(rce_b))
|
||||
assert(rq_b == rq_b_e);
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ always @(posedge clk) begin
|
|||
read_addr <= counter;
|
||||
read_val <= mem[counter];
|
||||
end else begin
|
||||
did_read <= 1'b0;
|
||||
did_read <= 1'b0;
|
||||
end
|
||||
|
||||
if (!done)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
|
|||
parameter WIDTHA = 4;
|
||||
parameter SIZEA = 1024;
|
||||
parameter ADDRWIDTHA = 10;
|
||||
|
||||
|
||||
parameter WIDTHB = 16;
|
||||
parameter SIZEB = 256;
|
||||
parameter ADDRWIDTHB = 8;
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ hierarchy -top block_ram
|
|||
synth_xilinx -top block_ram -noiopad
|
||||
cd block_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
|
||||
# Check that distributed memory without parameters is not modified
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
@ -12,7 +12,7 @@ hierarchy -top distributed_ram
|
|||
synth_xilinx -top distributed_ram -noiopad
|
||||
cd distributed_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:RAM32M
|
||||
|
||||
|
||||
# Set ram_style distributed to blockram memory; will be implemented as distributed
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
@ -20,7 +20,7 @@ setattr -set ram_style "distributed" block_ram/m:*
|
|||
synth_xilinx -top block_ram -noiopad
|
||||
cd block_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 16 t:RAM256X1S
|
||||
|
||||
|
||||
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
@ -28,7 +28,7 @@ setattr -set logic_block 1 block_ram/m:*
|
|||
synth_xilinx -top block_ram -noiopad
|
||||
cd block_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
|
||||
|
||||
# Set ram_style block to a distributed memory; will be implemented as blockram
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1
|
|||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_style "block" m:memory
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
|
|
@ -58,7 +58,7 @@ select -assert-count 1 t:RAMB18E1
|
|||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
|
|
|
|||
|
|
@ -3,13 +3,13 @@ module led_blink (
|
|||
input clk,
|
||||
output ledc
|
||||
);
|
||||
|
||||
|
||||
reg [6:0] led_counter = 0;
|
||||
always @( posedge clk ) begin
|
||||
led_counter <= led_counter + 1;
|
||||
end
|
||||
assign ledc = !led_counter[ 6:3 ];
|
||||
|
||||
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
|
|||
reg [DEPTH-1:0] r = INIT;
|
||||
wire clk = C ^ CLKPOL;
|
||||
always @(posedge C)
|
||||
if (E)
|
||||
if (E)
|
||||
r <= { r[DEPTH-2:0], D };
|
||||
assign Q = r[L];
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -6,19 +6,19 @@
|
|||
|
||||
module GrayCounter
|
||||
#(parameter COUNTER_WIDTH = 4)
|
||||
|
||||
|
||||
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
|
||||
|
||||
|
||||
input wire Enable_in, //Count enable.
|
||||
input wire Clear_in, //Count reset.
|
||||
|
||||
|
||||
input wire Clk);
|
||||
|
||||
/////////Internal connections & variables///////
|
||||
reg [COUNTER_WIDTH-1:0] BinaryCount;
|
||||
|
||||
/////////Code///////////////////////
|
||||
|
||||
|
||||
always @ (posedge Clk)
|
||||
if (Clear_in) begin
|
||||
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
|
||||
|
|
@ -29,5 +29,5 @@ module GrayCounter
|
|||
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
|
||||
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -3,32 +3,32 @@
|
|||
// orginally coded by WD Peterson in VHDL.
|
||||
//----------------------------------------------------
|
||||
module arbiter (
|
||||
clk,
|
||||
rst,
|
||||
req3,
|
||||
req2,
|
||||
req1,
|
||||
req0,
|
||||
gnt3,
|
||||
gnt2,
|
||||
gnt1,
|
||||
gnt0
|
||||
clk,
|
||||
rst,
|
||||
req3,
|
||||
req2,
|
||||
req1,
|
||||
req0,
|
||||
gnt3,
|
||||
gnt2,
|
||||
gnt1,
|
||||
gnt0
|
||||
);
|
||||
// --------------Port Declaration-----------------------
|
||||
input clk;
|
||||
input rst;
|
||||
input req3;
|
||||
input req2;
|
||||
input req1;
|
||||
input req0;
|
||||
output gnt3;
|
||||
output gnt2;
|
||||
output gnt1;
|
||||
output gnt0;
|
||||
// --------------Port Declaration-----------------------
|
||||
input clk;
|
||||
input rst;
|
||||
input req3;
|
||||
input req2;
|
||||
input req1;
|
||||
input req0;
|
||||
output gnt3;
|
||||
output gnt2;
|
||||
output gnt1;
|
||||
output gnt0;
|
||||
|
||||
//--------------Internal Registers----------------------
|
||||
wire [1:0] gnt ;
|
||||
wire comreq ;
|
||||
wire [1:0] gnt ;
|
||||
wire comreq ;
|
||||
wire beg ;
|
||||
wire [1:0] lgnt ;
|
||||
wire lcomreq ;
|
||||
|
|
@ -41,14 +41,14 @@ reg lmask0 ;
|
|||
reg lmask1 ;
|
||||
reg ledge ;
|
||||
|
||||
//--------------Code Starts Here-----------------------
|
||||
//--------------Code Starts Here-----------------------
|
||||
always @ (posedge clk)
|
||||
if (rst) begin
|
||||
lgnt0 <= 0;
|
||||
lgnt1 <= 0;
|
||||
lgnt2 <= 0;
|
||||
lgnt3 <= 0;
|
||||
end else begin
|
||||
end else begin
|
||||
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
|
||||
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
|
||||
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
|
||||
|
|
@ -69,18 +69,18 @@ end else begin
|
|||
| (~lcomreq & lmask1 & ~lmask0 & req3)
|
||||
| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
|
||||
| ( lcomreq & lgnt3);
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------
|
||||
// lasmask state machine.
|
||||
//----------------------------------------------------
|
||||
assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
begin
|
||||
lasmask <= (beg & ~ledge & ~lasmask);
|
||||
ledge <= (beg & ~ledge & lasmask)
|
||||
ledge <= (beg & ~ledge & lasmask)
|
||||
| (beg & ledge & ~lasmask);
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------
|
||||
// comreq logic.
|
||||
|
|
@ -108,7 +108,7 @@ end else if(lasmask) begin
|
|||
end else begin
|
||||
lmask1 <= lmask1;
|
||||
lmask0 <= lmask0;
|
||||
end
|
||||
end
|
||||
|
||||
assign comreq = lcomreq;
|
||||
assign gnt = lgnt;
|
||||
|
|
|
|||
|
|
@ -6,10 +6,10 @@ reg req3 = 0;
|
|||
reg req2 = 0;
|
||||
reg req1 = 0;
|
||||
reg req0 = 0;
|
||||
wire gnt3;
|
||||
wire gnt2;
|
||||
wire gnt1;
|
||||
wire gnt0;
|
||||
wire gnt3;
|
||||
wire gnt2;
|
||||
wire gnt1;
|
||||
wire gnt0;
|
||||
|
||||
// Clock generator
|
||||
always #1 clk = ~clk;
|
||||
|
|
@ -41,20 +41,20 @@ initial begin
|
|||
req0 <= 0;
|
||||
repeat (1) @ (posedge clk);
|
||||
#10 $finish;
|
||||
end
|
||||
end
|
||||
|
||||
// Connect the DUT
|
||||
arbiter U (
|
||||
clk,
|
||||
rst,
|
||||
req3,
|
||||
req2,
|
||||
req1,
|
||||
req0,
|
||||
gnt3,
|
||||
gnt2,
|
||||
gnt1,
|
||||
gnt0
|
||||
clk,
|
||||
rst,
|
||||
req3,
|
||||
req2,
|
||||
req1,
|
||||
req0,
|
||||
gnt3,
|
||||
gnt2,
|
||||
gnt1,
|
||||
gnt0
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -9,18 +9,18 @@ clk , // Cam clock
|
|||
cam_enable , // Cam enable
|
||||
cam_data_in , // Cam data to match
|
||||
cam_hit_out , // Cam match has happened
|
||||
cam_addr_out // Cam output address
|
||||
cam_addr_out // Cam output address
|
||||
);
|
||||
|
||||
parameter ADDR_WIDTH = 8;
|
||||
parameter DEPTH = 1 << ADDR_WIDTH;
|
||||
//------------Input Ports--------------
|
||||
input clk;
|
||||
input cam_enable;
|
||||
input [DEPTH-1:0] cam_data_in;
|
||||
input clk;
|
||||
input cam_enable;
|
||||
input [DEPTH-1:0] cam_data_in;
|
||||
//----------Output Ports--------------
|
||||
output cam_hit_out;
|
||||
output [ADDR_WIDTH-1:0] cam_addr_out;
|
||||
output cam_hit_out;
|
||||
output [ADDR_WIDTH-1:0] cam_addr_out;
|
||||
//------------Internal Variables--------
|
||||
reg [ADDR_WIDTH-1:0] cam_addr_out;
|
||||
reg cam_hit_out;
|
||||
|
|
@ -46,7 +46,7 @@ always @(cam_data_in) begin
|
|||
end
|
||||
end
|
||||
|
||||
// Register the outputs
|
||||
// Register the outputs
|
||||
always @(posedge clk) begin
|
||||
if (cam_enable) begin
|
||||
cam_hit_out <= cam_hit_combo;
|
||||
|
|
@ -57,4 +57,4 @@ always @(posedge clk) begin
|
|||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
//-----------------------------------------------------
|
||||
|
||||
module clk_div (clk_in, enable,reset, clk_out);
|
||||
// --------------Port Declaration-----------------------
|
||||
// --------------Port Declaration-----------------------
|
||||
input clk_in ;
|
||||
input reset ;
|
||||
input enable ;
|
||||
|
|
@ -16,12 +16,12 @@ module clk_div (clk_in, enable,reset, clk_out);
|
|||
wire enable ;
|
||||
//--------------Internal Registers----------------------
|
||||
reg clk_out ;
|
||||
//--------------Code Starts Here-----------------------
|
||||
always @ (posedge clk_in)
|
||||
if (reset) begin
|
||||
//--------------Code Starts Here-----------------------
|
||||
always @ (posedge clk_in)
|
||||
if (reset) begin
|
||||
clk_out <= 1'b0;
|
||||
end else if (enable) begin
|
||||
clk_out <= !clk_out ;
|
||||
clk_out <= !clk_out ;
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ reg toggle2 ;
|
|||
|
||||
//--------------Code Starts Here-----------------------
|
||||
always @ (posedge clk_in)
|
||||
if (enable == 1'b0) begin
|
||||
if (enable == 1'b0) begin
|
||||
counter1 <= 4'b0;
|
||||
toggle1 <= 0;
|
||||
end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
|
||||
|
|
@ -37,7 +37,7 @@ end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
|
|||
end else begin
|
||||
counter1 <= counter1 + 1;
|
||||
end
|
||||
|
||||
|
||||
always @ (negedge clk_in)
|
||||
if (enable == 1'b0) begin
|
||||
counter2 <= 4'b0;
|
||||
|
|
|
|||
|
|
@ -6,14 +6,14 @@
|
|||
//-----------------------------------------------------
|
||||
module decoder_using_assign (
|
||||
binary_in , // 4 bit binary input
|
||||
decoder_out , // 16-bit out
|
||||
decoder_out , // 16-bit out
|
||||
enable // Enable for the decoder
|
||||
);
|
||||
input [3:0] binary_in ;
|
||||
input enable ;
|
||||
output [15:0] decoder_out ;
|
||||
|
||||
wire [15:0] decoder_out ;
|
||||
input enable ;
|
||||
output [15:0] decoder_out ;
|
||||
|
||||
wire [15:0] decoder_out ;
|
||||
|
||||
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
|
||||
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@
|
|||
module dff_async_reset (
|
||||
data , // Data Input
|
||||
clk , // Clock Input
|
||||
reset , // Reset input
|
||||
reset , // Reset input
|
||||
q // Q output
|
||||
);
|
||||
//-----------Input Ports---------------
|
||||
input data, clk, reset ;
|
||||
input data, clk, reset ;
|
||||
|
||||
//-----------Output Ports---------------
|
||||
output q;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ reset , // Reset input
|
|||
q // Q output
|
||||
);
|
||||
//-----------Input Ports---------------
|
||||
input data, clk, reset ;
|
||||
input data, clk, reset ;
|
||||
|
||||
//-----------Output Ports---------------
|
||||
output q;
|
||||
|
|
|
|||
|
|
@ -10,31 +10,31 @@ encoder_in , // 16-bit Input
|
|||
enable // Enable for the encoder
|
||||
);
|
||||
output [3:0] binary_out ;
|
||||
input enable ;
|
||||
input [15:0] encoder_in ;
|
||||
|
||||
input enable ;
|
||||
input [15:0] encoder_in ;
|
||||
|
||||
reg [3:0] binary_out ;
|
||||
|
||||
|
||||
always @ (enable or encoder_in)
|
||||
begin
|
||||
binary_out = 0;
|
||||
if (enable) begin
|
||||
case (encoder_in)
|
||||
16'h0002 : binary_out = 1;
|
||||
16'h0004 : binary_out = 2;
|
||||
16'h0008 : binary_out = 3;
|
||||
case (encoder_in)
|
||||
16'h0002 : binary_out = 1;
|
||||
16'h0004 : binary_out = 2;
|
||||
16'h0008 : binary_out = 3;
|
||||
16'h0010 : binary_out = 4;
|
||||
16'h0020 : binary_out = 5;
|
||||
16'h0040 : binary_out = 6;
|
||||
16'h0080 : binary_out = 7;
|
||||
16'h0020 : binary_out = 5;
|
||||
16'h0040 : binary_out = 6;
|
||||
16'h0080 : binary_out = 7;
|
||||
16'h0100 : binary_out = 8;
|
||||
16'h0200 : binary_out = 9;
|
||||
16'h0400 : binary_out = 10;
|
||||
16'h0800 : binary_out = 11;
|
||||
16'h1000 : binary_out = 12;
|
||||
16'h2000 : binary_out = 13;
|
||||
16'h4000 : binary_out = 14;
|
||||
16'h8000 : binary_out = 15;
|
||||
16'h0400 : binary_out = 10;
|
||||
16'h0800 : binary_out = 11;
|
||||
16'h1000 : binary_out = 12;
|
||||
16'h2000 : binary_out = 13;
|
||||
16'h4000 : binary_out = 14;
|
||||
16'h8000 : binary_out = 15;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -8,51 +8,51 @@ module encoder_using_if(
|
|||
binary_out , // 4 bit binary output
|
||||
encoder_in , // 16-bit input
|
||||
enable // Enable for the encoder
|
||||
);
|
||||
);
|
||||
//-----------Output Ports---------------
|
||||
output [3:0] binary_out ;
|
||||
//-----------Input Ports---------------
|
||||
input enable ;
|
||||
input [15:0] encoder_in ;
|
||||
input enable ;
|
||||
input [15:0] encoder_in ;
|
||||
//------------Internal Variables--------
|
||||
reg [3:0] binary_out ;
|
||||
reg [3:0] binary_out ;
|
||||
//-------------Code Start-----------------
|
||||
always @ (enable or encoder_in)
|
||||
begin
|
||||
binary_out = 0;
|
||||
begin
|
||||
binary_out = 0;
|
||||
if (enable) begin
|
||||
if (encoder_in == 16'h0002) begin
|
||||
binary_out = 1;
|
||||
end if (encoder_in == 16'h0004) begin
|
||||
binary_out = 2;
|
||||
end if (encoder_in == 16'h0008) begin
|
||||
binary_out = 3;
|
||||
end if (encoder_in == 16'h0010) begin
|
||||
binary_out = 4;
|
||||
end if (encoder_in == 16'h0020) begin
|
||||
binary_out = 5;
|
||||
end if (encoder_in == 16'h0040) begin
|
||||
binary_out = 6;
|
||||
end if (encoder_in == 16'h0080) begin
|
||||
binary_out = 7;
|
||||
end if (encoder_in == 16'h0100) begin
|
||||
binary_out = 8;
|
||||
end if (encoder_in == 16'h0200) begin
|
||||
binary_out = 9;
|
||||
end if (encoder_in == 16'h0400) begin
|
||||
binary_out = 10;
|
||||
end if (encoder_in == 16'h0800) begin
|
||||
binary_out = 11;
|
||||
end if (encoder_in == 16'h0004) begin
|
||||
binary_out = 2;
|
||||
end if (encoder_in == 16'h0008) begin
|
||||
binary_out = 3;
|
||||
end if (encoder_in == 16'h0010) begin
|
||||
binary_out = 4;
|
||||
end if (encoder_in == 16'h0020) begin
|
||||
binary_out = 5;
|
||||
end if (encoder_in == 16'h0040) begin
|
||||
binary_out = 6;
|
||||
end if (encoder_in == 16'h0080) begin
|
||||
binary_out = 7;
|
||||
end if (encoder_in == 16'h0100) begin
|
||||
binary_out = 8;
|
||||
end if (encoder_in == 16'h0200) begin
|
||||
binary_out = 9;
|
||||
end if (encoder_in == 16'h0400) begin
|
||||
binary_out = 10;
|
||||
end if (encoder_in == 16'h0800) begin
|
||||
binary_out = 11;
|
||||
end if (encoder_in == 16'h1000) begin
|
||||
binary_out = 12;
|
||||
end if (encoder_in == 16'h2000) begin
|
||||
binary_out = 12;
|
||||
end if (encoder_in == 16'h2000) begin
|
||||
binary_out = 13;
|
||||
end if (encoder_in == 16'h4000) begin
|
||||
binary_out = 14;
|
||||
end if (encoder_in == 16'h8000) begin
|
||||
binary_out = 15;
|
||||
end if (encoder_in == 16'h4000) begin
|
||||
binary_out = 14;
|
||||
end if (encoder_in == 16'h8000) begin
|
||||
binary_out = 15;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -10,24 +10,24 @@ module gray_counter (
|
|||
clk , // clock
|
||||
rst // active hight reset
|
||||
);
|
||||
|
||||
|
||||
//------------Input Ports--------------
|
||||
input clk, rst, enable;
|
||||
input clk, rst, enable;
|
||||
//----------Output Ports----------------
|
||||
output [ 7:0] out;
|
||||
//------------Internal Variables--------
|
||||
wire [7:0] out;
|
||||
reg [7:0] count;
|
||||
//-------------Code Starts Here---------
|
||||
always @ (posedge clk)
|
||||
if (rst)
|
||||
count <= 0;
|
||||
else if (enable)
|
||||
count <= count + 1;
|
||||
|
||||
assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
|
||||
count[5]),(count[5] ^ count[4]), (count[4] ^
|
||||
count[3]),(count[3] ^ count[2]), (count[2] ^
|
||||
always @ (posedge clk)
|
||||
if (rst)
|
||||
count <= 0;
|
||||
else if (enable)
|
||||
count <= count + 1;
|
||||
|
||||
assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
|
||||
count[5]),(count[5] ^ count[4]), (count[4] ^
|
||||
count[3]),(count[3] ^ count[2]), (count[2] ^
|
||||
count[1]),(count[1] ^ count[0]) };
|
||||
|
||||
endmodule
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -30,6 +30,6 @@ end else if (enable) begin
|
|||
out[4],out[3],
|
||||
out[2],out[1],
|
||||
out[0], linear_feedback};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // End Of Module counter
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
`define WIDTH 8
|
||||
`define WIDTH 8
|
||||
module lfsr_updown (
|
||||
clk , // Clock input
|
||||
reset , // Reset input
|
||||
|
|
@ -10,7 +10,7 @@ overflow // Overflow output
|
|||
|
||||
input clk;
|
||||
input reset;
|
||||
input enable;
|
||||
input enable;
|
||||
input up_down;
|
||||
|
||||
output [`WIDTH-1 : 0] count;
|
||||
|
|
@ -18,11 +18,11 @@ overflow // Overflow output
|
|||
|
||||
reg [`WIDTH-1 : 0] count;
|
||||
|
||||
assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :
|
||||
assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :
|
||||
(count == {1'b1, {`WIDTH-1{1'b0}}}) ;
|
||||
|
||||
always @(posedge clk)
|
||||
if (reset)
|
||||
if (reset)
|
||||
count <= {`WIDTH{1'b0}};
|
||||
else if (enable) begin
|
||||
if (up_down) begin
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@ reg mux_out;
|
|||
//-------------Code Starts Here---------
|
||||
always @ (sel or din_0 or din_1)
|
||||
begin : MUX
|
||||
case(sel )
|
||||
case(sel )
|
||||
1'b0 : mux_out = din_0;
|
||||
1'b1 : mux_out = din_1;
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule //End Of Module mux
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ output [7:0] out;
|
|||
input enable, clk, reset;
|
||||
|
||||
//------------Internal Variables--------
|
||||
reg [7:0] out;
|
||||
reg [7:0] out;
|
||||
|
||||
//-------------Code Starts Here-------
|
||||
always @ (posedge clk)
|
||||
|
|
@ -28,4 +28,4 @@ end else if (enable) begin
|
|||
out[2],out[1],out[0],out[7]};
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ module parallel_crc_ccitt (
|
|||
clk ,
|
||||
reset ,
|
||||
enable ,
|
||||
init ,
|
||||
data_in ,
|
||||
init ,
|
||||
data_in ,
|
||||
crc_out
|
||||
);
|
||||
//-----------Input Ports---------------
|
||||
|
|
|
|||
|
|
@ -9,13 +9,13 @@ data_in , // 8 bit data in
|
|||
parity_out // 1 bit parity out
|
||||
);
|
||||
output parity_out ;
|
||||
input [7:0] data_in ;
|
||||
|
||||
input [7:0] data_in ;
|
||||
|
||||
wire parity_out ;
|
||||
|
||||
assign parity_out = (data_in[0] ^ data_in[1]) ^
|
||||
(data_in[2] ^ data_in[3]) ^
|
||||
(data_in[4] ^ data_in[5]) ^
|
||||
|
||||
assign parity_out = (data_in[0] ^ data_in[1]) ^
|
||||
(data_in[2] ^ data_in[3]) ^
|
||||
(data_in[4] ^ data_in[5]) ^
|
||||
(data_in[6] ^ data_in[7]);
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ data_in , // 8 bit data in
|
|||
parity_out // 1 bit parity out
|
||||
);
|
||||
output parity_out ;
|
||||
input [7:0] data_in ;
|
||||
|
||||
assign parity_out = ^data_in;
|
||||
input [7:0] data_in ;
|
||||
|
||||
assign parity_out = ^data_in;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -9,21 +9,21 @@ data_in , // 8 bit data in
|
|||
parity_out // 1 bit parity out
|
||||
);
|
||||
output parity_out ;
|
||||
input [7:0] data_in ;
|
||||
|
||||
wire parity_out ;
|
||||
input [7:0] data_in ;
|
||||
|
||||
wire parity_out ;
|
||||
|
||||
function parity;
|
||||
input [31:0] data;
|
||||
input [31:0] data;
|
||||
begin
|
||||
parity = (data_in[0] ^ data_in[1]) ^
|
||||
(data_in[2] ^ data_in[3]) ^
|
||||
(data_in[4] ^ data_in[5]) ^
|
||||
parity = (data_in[0] ^ data_in[1]) ^
|
||||
(data_in[2] ^ data_in[3]) ^
|
||||
(data_in[4] ^ data_in[5]) ^
|
||||
(data_in[6] ^ data_in[7]);
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
assign parity_out = parity(data_in);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -6,31 +6,31 @@
|
|||
//-----------------------------------------------------
|
||||
module pri_encoder_using_assign (
|
||||
binary_out , // 4 bit binary output
|
||||
encoder_in , // 16-bit input
|
||||
encoder_in , // 16-bit input
|
||||
enable // Enable for the encoder
|
||||
);
|
||||
|
||||
output [3:0] binary_out ;
|
||||
input enable ;
|
||||
input [15:0] encoder_in ;
|
||||
input enable ;
|
||||
input [15:0] encoder_in ;
|
||||
|
||||
wire [3:0] binary_out ;
|
||||
|
||||
assign binary_out = (!enable) ? 0 : (
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
|
||||
(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
|
||||
(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
|
||||
(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
|
||||
(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
|
||||
(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
|
||||
(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
|
||||
(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
|
||||
(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
|
||||
(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
|
||||
|
||||
endmodule
|
||||
assign binary_out = (!enable) ? 0 : (
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
|
||||
(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
|
||||
(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
|
||||
(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
|
||||
(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
|
||||
(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
|
||||
(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
|
||||
(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
|
||||
(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
|
||||
(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
|
||||
(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
module rom_using_case (
|
||||
address , // Address input
|
||||
data , // Data output
|
||||
read_en , // Read Enable
|
||||
read_en , // Read Enable
|
||||
ce // Chip Enable
|
||||
);
|
||||
input [3:0] address;
|
||||
|
|
@ -16,7 +16,7 @@ input read_en;
|
|||
input ce;
|
||||
|
||||
reg [7:0] data ;
|
||||
|
||||
|
||||
always @ (ce or read_en or address)
|
||||
begin
|
||||
case (address)
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ module serial_crc_ccitt (
|
|||
clk ,
|
||||
reset ,
|
||||
enable ,
|
||||
init ,
|
||||
data_in ,
|
||||
init ,
|
||||
data_in ,
|
||||
crc_out
|
||||
);
|
||||
//-----------Input Ports---------------
|
||||
|
|
@ -49,6 +49,6 @@ end else if (enable) begin
|
|||
lfsr[14] <= lfsr[13];
|
||||
lfsr[15] <= lfsr[14];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ reset , // Reset input
|
|||
q // Q output
|
||||
);
|
||||
//-----------Input Ports---------------
|
||||
input data, clk, reset ;
|
||||
input data, clk, reset ;
|
||||
//-----------Output Ports---------------
|
||||
output q;
|
||||
//------------Internal Variables--------
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ reset , // Reset input
|
|||
q // Q output
|
||||
);
|
||||
//-----------Input Ports---------------
|
||||
input data, clk, reset ;
|
||||
input data, clk, reset ;
|
||||
//-----------Output Ports---------------
|
||||
output q;
|
||||
//------------Internal Variables--------
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
//-----------------------------------------------------
|
||||
// Design Name : uart
|
||||
// Design Name : uart
|
||||
// File Name : uart.v
|
||||
// Function : Simple UART
|
||||
// Coder : Deepak Kumar Tala
|
||||
|
|
@ -34,7 +34,7 @@ input rx_enable ;
|
|||
input rx_in ;
|
||||
output rx_empty ;
|
||||
|
||||
// Internal Variables
|
||||
// Internal Variables
|
||||
reg [7:0] tx_reg ;
|
||||
reg tx_empty ;
|
||||
reg tx_over_run ;
|
||||
|
|
@ -43,7 +43,7 @@ reg tx_out ;
|
|||
reg [7:0] rx_reg ;
|
||||
reg [7:0] rx_data ;
|
||||
reg [3:0] rx_sample_cnt ;
|
||||
reg [3:0] rx_cnt ;
|
||||
reg [3:0] rx_cnt ;
|
||||
reg rx_frame_err ;
|
||||
reg rx_over_run ;
|
||||
reg rx_empty ;
|
||||
|
|
@ -54,7 +54,7 @@ reg rx_busy ;
|
|||
// UART RX Logic
|
||||
always @ (posedge rxclk or posedge reset)
|
||||
if (reset) begin
|
||||
rx_reg <= 0;
|
||||
rx_reg <= 0;
|
||||
rx_data <= 0;
|
||||
rx_sample_cnt <= 0;
|
||||
rx_cnt <= 0;
|
||||
|
|
@ -89,7 +89,7 @@ end else begin
|
|||
if ((rx_d2 == 1) && (rx_cnt == 0)) begin
|
||||
rx_busy <= 0;
|
||||
end else begin
|
||||
rx_cnt <= rx_cnt + 1;
|
||||
rx_cnt <= rx_cnt + 1;
|
||||
// Start storing the rx data
|
||||
if (rx_cnt > 0 && rx_cnt < 9) begin
|
||||
rx_reg[rx_cnt - 1] <= rx_d2;
|
||||
|
|
@ -107,8 +107,8 @@ end else begin
|
|||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
if (!rx_enable) begin
|
||||
rx_busy <= 0;
|
||||
|
|
|
|||
|
|
@ -25,4 +25,4 @@ end else if (enable) begin
|
|||
end
|
||||
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ reset // reset input
|
|||
);
|
||||
//----------Output Ports--------------
|
||||
output [7:0] out;
|
||||
//------------Input Ports--------------
|
||||
//------------Input Ports--------------
|
||||
input [7:0] data;
|
||||
input load, enable, clk, reset;
|
||||
//------------Internal Variables--------
|
||||
|
|
@ -28,5 +28,5 @@ end else if (load) begin
|
|||
end else if (enable) begin
|
||||
out <= out + 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ reset // reset input
|
|||
);
|
||||
//----------Output Ports--------------
|
||||
output [7:0] out;
|
||||
//------------Input Ports--------------
|
||||
//------------Input Ports--------------
|
||||
input up_down, clk, reset;
|
||||
//------------Internal Variables--------
|
||||
reg [7:0] out;
|
||||
|
|
@ -26,4 +26,4 @@ end else begin
|
|||
out <= out - 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -22,28 +22,28 @@ output [7:0] data_out_ack3, data_out_ack4, data_out_ack5;
|
|||
(* gentb_clock *)
|
||||
wire clk;
|
||||
|
||||
switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0),
|
||||
.data_in_valid(data_in_valid0), .data_out(data_out0),
|
||||
switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0),
|
||||
.data_in_valid(data_in_valid0), .data_out(data_out0),
|
||||
.data_out_ack(data_out_ack0));
|
||||
|
||||
switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1),
|
||||
.data_in_valid(data_in_valid1), .data_out(data_out1),
|
||||
switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1),
|
||||
.data_in_valid(data_in_valid1), .data_out(data_out1),
|
||||
.data_out_ack(data_out_ack1));
|
||||
|
||||
switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2),
|
||||
switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2),
|
||||
.data_in_valid(data_in_valid2), .data_out(data_out2), .
|
||||
data_out_ack(data_out_ack2));
|
||||
|
||||
switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3),
|
||||
.data_in_valid(data_in_valid3), .data_out(data_out3),
|
||||
switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3),
|
||||
.data_in_valid(data_in_valid3), .data_out(data_out3),
|
||||
.data_out_ack(data_out_ack3));
|
||||
|
||||
switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4),
|
||||
.data_in_valid(data_in_valid4), .data_out(data_out4),
|
||||
switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4),
|
||||
.data_in_valid(data_in_valid4), .data_out(data_out4),
|
||||
.data_out_ack(data_out_ack4));
|
||||
|
||||
switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5),
|
||||
.data_in_valid(data_in_valid5), .data_out(data_out5),
|
||||
switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5),
|
||||
.data_in_valid(data_in_valid5), .data_out(data_out5),
|
||||
.data_out_ack(data_out_ack5));
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@ module asyn_reset(clk,reset,a,c);
|
|||
input clk;
|
||||
input reset;
|
||||
input a;
|
||||
output c;
|
||||
output c;
|
||||
|
||||
wire clk;
|
||||
wire reset;
|
||||
wire a;
|
||||
wire reset;
|
||||
wire a;
|
||||
reg c;
|
||||
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
if ( reset == 1'b1) begin
|
||||
c <= 0;
|
||||
|
|
|
|||
|
|
@ -2,16 +2,16 @@ module blocking (clk,a,c);
|
|||
input clk;
|
||||
input a;
|
||||
output c;
|
||||
|
||||
|
||||
wire clk;
|
||||
wire a;
|
||||
reg c;
|
||||
reg b;
|
||||
|
||||
|
||||
always @ (posedge clk )
|
||||
begin
|
||||
b = a;
|
||||
c = b;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ reset , // Active high, syn reset
|
|||
req_0 , // Request 0
|
||||
req_1 , // Request 1
|
||||
gnt_0 , // Grant 0
|
||||
gnt_1
|
||||
gnt_1
|
||||
);
|
||||
//-------------Input Ports-----------------------------
|
||||
input clock,reset,req_0,req_1;
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ reset , // Active high, syn reset
|
|||
req_0 , // Request 0
|
||||
req_1 , // Request 1
|
||||
gnt_0 , // Grant 0
|
||||
gnt_1
|
||||
gnt_1
|
||||
);
|
||||
//-------------Input Ports-----------------------------
|
||||
input clock,reset,req_0,req_1;
|
||||
|
|
@ -29,7 +29,7 @@ wire [SIZE-1:0] next_state ;// combo part of FSM
|
|||
assign next_state = fsm_function(state, req_0, req_1);
|
||||
//----------Function for Combo Logic-----------------
|
||||
function [SIZE-1:0] fsm_function;
|
||||
input [SIZE-1:0] state ;
|
||||
input [SIZE-1:0] state ;
|
||||
input req_0 ;
|
||||
input req_1 ;
|
||||
case(state)
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ reset , // Active high, syn reset
|
|||
req_0 , // Request 0
|
||||
req_1 , // Request 1
|
||||
gnt_0 , // Grant 0
|
||||
gnt_1
|
||||
gnt_1
|
||||
);
|
||||
//=============Input Ports=============================
|
||||
input clock,reset,req_0,req_1;
|
||||
|
|
|
|||
|
|
@ -2,16 +2,16 @@ module nonblocking (clk,a,c);
|
|||
input clk;
|
||||
input a;
|
||||
output c;
|
||||
|
||||
|
||||
wire clk;
|
||||
wire a;
|
||||
reg c;
|
||||
reg b;
|
||||
|
||||
|
||||
always @ (posedge clk )
|
||||
begin
|
||||
b <= a;
|
||||
c <= b;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ reg y;
|
|||
wire a, b;
|
||||
|
||||
always @ ( a or b)
|
||||
begin
|
||||
begin
|
||||
y = a & b;
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
module reg_seq_example( clk, reset, d, q);
|
||||
input clk, reset, d;
|
||||
output q;
|
||||
|
||||
|
||||
reg q;
|
||||
wire clk, reset, d;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
module syn_reset (clk,reset,a,c);
|
||||
input clk;
|
||||
input reset;
|
||||
input a;
|
||||
output c;
|
||||
input a;
|
||||
output c;
|
||||
|
||||
wire clk;
|
||||
wire reset;
|
||||
wire a;
|
||||
wire reset;
|
||||
wire a;
|
||||
reg c;
|
||||
|
||||
|
||||
always @ (posedge clk )
|
||||
if ( reset == 1'b1) begin
|
||||
c <= 0;
|
||||
end else begin
|
||||
c <= a;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ reg clk,reset,enable,q_in,data;
|
|||
always @ (posedge clk)
|
||||
if (reset) begin
|
||||
data <= 0;
|
||||
end else if (enable) begin
|
||||
end else if (enable) begin
|
||||
data <= q_in;
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ module bus_con (a,b, y);
|
|||
input [3:0] a, b;
|
||||
output [7:0] y;
|
||||
wire [7:0] y;
|
||||
|
||||
|
||||
assign y = {a,b};
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -15,11 +15,11 @@ input ci;
|
|||
// Output ports
|
||||
output sum;
|
||||
output co;
|
||||
// Data Types
|
||||
// Data Types
|
||||
wire a;
|
||||
wire b;
|
||||
wire ci;
|
||||
wire sum;
|
||||
wire co;
|
||||
wire co;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
module counter (clk, reset, enable, count);
|
||||
input clk, reset, enable;
|
||||
output [3:0] count;
|
||||
reg [3:0] count;
|
||||
reg [3:0] count;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset == 1'b1) begin
|
||||
|
|
@ -16,4 +16,4 @@ end else if ( enable == 1'b1) begin
|
|||
count <= count + 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ input d ,clk;
|
|||
output q, q_bar;
|
||||
wire d ,clk;
|
||||
reg q, q_bar;
|
||||
|
||||
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
q <= d;
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@ module decoder (in,out);
|
|||
input [2:0] in;
|
||||
output [7:0] out;
|
||||
wire [7:0] out;
|
||||
assign out = (in == 3'b000 ) ? 8'b0000_0001 :
|
||||
(in == 3'b001 ) ? 8'b0000_0010 :
|
||||
(in == 3'b010 ) ? 8'b0000_0100 :
|
||||
(in == 3'b011 ) ? 8'b0000_1000 :
|
||||
(in == 3'b100 ) ? 8'b0001_0000 :
|
||||
(in == 3'b101 ) ? 8'b0010_0000 :
|
||||
(in == 3'b110 ) ? 8'b0100_0000 :
|
||||
assign out = (in == 3'b000 ) ? 8'b0000_0001 :
|
||||
(in == 3'b001 ) ? 8'b0000_0010 :
|
||||
(in == 3'b010 ) ? 8'b0000_0100 :
|
||||
(in == 3'b011 ) ? 8'b0000_1000 :
|
||||
(in == 3'b100 ) ? 8'b0001_0000 :
|
||||
(in == 3'b101 ) ? 8'b0010_0000 :
|
||||
(in == 3'b110 ) ? 8'b0100_0000 :
|
||||
(in == 3'b111 ) ? 8'b1000_0000 : 8'h00;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ module decoder_always (in,out);
|
|||
input [2:0] in;
|
||||
output [7:0] out;
|
||||
reg [7:0] out;
|
||||
|
||||
|
||||
always @ (in)
|
||||
begin
|
||||
out = 0;
|
||||
|
|
@ -16,5 +16,5 @@ begin
|
|||
3'b111 : out = 8'b1000_0000;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -9,6 +9,6 @@ cl$k, // CLOCK input
|
|||
);
|
||||
|
||||
input d, cl$k, \reset* ;
|
||||
output q, \q~ ;
|
||||
output q, \q~ ;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ wire q;
|
|||
|
||||
// Here q_bar is not connected
|
||||
// We can connect ports in any order
|
||||
dff u0 (
|
||||
dff u0 (
|
||||
.q (q),
|
||||
.d (d),
|
||||
.clk (clk),
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ input enable ;
|
|||
//-------------Output Ports----------------------------
|
||||
output [3:0] counter_out ;
|
||||
//-------------Input ports Data Type-------------------
|
||||
// By rule all the input ports should be wires
|
||||
// By rule all the input ports should be wires
|
||||
wire clock ;
|
||||
wire reset ;
|
||||
wire enable ;
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ wire [3:0] counter_out;
|
|||
integer file;
|
||||
|
||||
// Initialize all variables
|
||||
initial begin
|
||||
initial begin
|
||||
file = $fopen(`outfile);
|
||||
$fdisplay (file, "time\t clk reset enable counter");
|
||||
$fdisplay (file, "time\t clk reset enable counter");
|
||||
#5 reset = 1; // Assert the reset
|
||||
#10 reset = 0; // De-assert the reset
|
||||
#10 enable = 1; // Assert enable
|
||||
|
|
@ -16,8 +16,8 @@ initial begin
|
|||
end
|
||||
|
||||
always @(negedge clock)
|
||||
$fdisplay (file, "%g\t %b %b %b %b",
|
||||
$time, clock, reset, enable, counter_out);
|
||||
$fdisplay (file, "%g\t %b %b %b %b",
|
||||
$time, clock, reset, enable, counter_out);
|
||||
|
||||
// Clock generator
|
||||
initial begin
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ module flif_flop (clk,reset, q, d);
|
|||
input clk, reset, d;
|
||||
output q;
|
||||
reg q;
|
||||
|
||||
|
||||
always @ (posedge clk )
|
||||
begin
|
||||
if (reset == 1) begin
|
||||
|
|
@ -11,5 +11,5 @@ begin
|
|||
q <= d;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -20,13 +20,13 @@ input req_3 ; // Active high request from agent 3
|
|||
output gnt_0 ; // Active high grant to agent 0
|
||||
output gnt_1 ; // Active high grant to agent 1
|
||||
output gnt_2 ; // Active high grant to agent 2
|
||||
output gnt_3 ; // Active high grant to agent
|
||||
output gnt_3 ; // Active high grant to agent
|
||||
|
||||
// Internal Variables
|
||||
reg gnt_0 ; // Active high grant to agent 0
|
||||
reg gnt_1 ; // Active high grant to agent 1
|
||||
reg gnt_2 ; // Active high grant to agent 2
|
||||
reg gnt_3 ; // Active high grant to agent
|
||||
reg gnt_3 ; // Active high grant to agent
|
||||
|
||||
parameter [2:0] IDLE = 3'b000;
|
||||
parameter [2:0] GNT0 = 3'b001;
|
||||
|
|
@ -37,7 +37,7 @@ parameter [2:0] GNT3 = 3'b100;
|
|||
reg [2:0] state, next_state;
|
||||
|
||||
always @ (state or req_0 or req_1 or req_2 or req_3)
|
||||
begin
|
||||
begin
|
||||
next_state = 0;
|
||||
case(state)
|
||||
IDLE : if (req_0 == 1'b1) begin
|
||||
|
|
@ -50,7 +50,7 @@ begin
|
|||
next_state= GNT3;
|
||||
end else begin
|
||||
next_state = IDLE;
|
||||
end
|
||||
end
|
||||
GNT0 : if (req_0 == 1'b0) begin
|
||||
next_state = IDLE;
|
||||
end else begin
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
module testbench();
|
||||
reg clock = 0 , reset ;
|
||||
reg req_0 , req_1 , req_2 , req_3;
|
||||
reg req_0 , req_1 , req_2 , req_3;
|
||||
wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
|
||||
integer file;
|
||||
|
||||
|
|
@ -29,7 +29,7 @@ initial begin
|
|||
end
|
||||
|
||||
always @(negedge clock)
|
||||
$fdisplay(file, "%g\t %b %b %b %b %b %b %b %b",
|
||||
$fdisplay(file, "%g\t %b %b %b %b %b %b %b %b",
|
||||
$time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
|
||||
|
||||
initial begin
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ module muliply (a,product);
|
|||
input [3:0] a;
|
||||
output [4:0] product;
|
||||
wire [4:0] product;
|
||||
|
||||
|
||||
assign product = a << 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ module mux_21 (a,b,sel,y);
|
|||
output y;
|
||||
input sel;
|
||||
wire y;
|
||||
|
||||
|
||||
assign y = (sel) ? b : a;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ wire in;
|
|||
|
||||
// one output Buffer gate
|
||||
buf u_buf0 (out,in);
|
||||
// four output Buffer gate
|
||||
// four output Buffer gate
|
||||
buf u_buf1 (out_0, out_1, out_2, out_3, in);
|
||||
// three output Invertor gate
|
||||
// three output Invertor gate
|
||||
not u_not0 (out_a, out_b, out_c, in);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ wire clk,reset,enable, up_en, down_en;
|
|||
always @ (posedge clk)
|
||||
// If reset is asserted
|
||||
if (reset == 1'b0) begin
|
||||
counter <= 4'b0000;
|
||||
counter <= 4'b0000;
|
||||
end else begin
|
||||
// If counter is enable and up count is mode
|
||||
if (enable == 1'b1 && up_en == 1'b1) begin
|
||||
|
|
@ -15,7 +15,7 @@ end else begin
|
|||
// If counter is enable and down count is mode
|
||||
if (enable == 1'b1 && down_en == 1'b1) begin
|
||||
counter <= counter - 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
//-----------------------------------------------------
|
||||
module parity (
|
||||
a , // First input
|
||||
b , // Second input
|
||||
b , // Second input
|
||||
c , // Third Input
|
||||
d , // Fourth Input
|
||||
y // Parity output
|
||||
|
|
@ -38,4 +38,4 @@ xor u1 (out_1,c,d);
|
|||
|
||||
xor u2 (y,out_0,out_1);
|
||||
|
||||
endmodule // End Of Module parity
|
||||
endmodule // End Of Module parity
|
||||
|
|
|
|||
|
|
@ -6,6 +6,6 @@ wire enable,din;
|
|||
always @ (enable or din)
|
||||
if (enable) begin
|
||||
latch <= din;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ module tri_buf (a,b,enable);
|
|||
output b;
|
||||
input enable;
|
||||
wire b;
|
||||
|
||||
|
||||
assign b = (enable) ? a : 1'bz;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ output q;
|
|||
reg q;
|
||||
|
||||
always @ (posedge x or posedge y)
|
||||
if (x)
|
||||
if (x)
|
||||
q <= 1'b0;
|
||||
else
|
||||
q <= d;
|
||||
|
|
|
|||
|
|
@ -13,11 +13,11 @@ module \ff_with_en_and_sync_reset
|
|||
switch \reset
|
||||
case 1'1
|
||||
assign $0\q[0:0] 1'0
|
||||
case
|
||||
case
|
||||
switch \enable
|
||||
case 1'1
|
||||
assign $0\q[0:0] \d [0]
|
||||
case
|
||||
case
|
||||
end
|
||||
end
|
||||
sync posedge \clock
|
||||
|
|
@ -29,11 +29,11 @@ module \ff_with_en_and_sync_reset
|
|||
switch \reset
|
||||
case 1'1
|
||||
assign $0\q[1:1] 1'0
|
||||
case
|
||||
case
|
||||
switch \enable
|
||||
case 1'1
|
||||
assign $0\q[1:1] \d [1]
|
||||
case
|
||||
case
|
||||
end
|
||||
end
|
||||
sync posedge \clock
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ void test_binary_operation(Operation &op)
|
|||
}
|
||||
|
||||
template<typename Operation>
|
||||
struct UnaryOperationWrapper : BinaryOperationBase
|
||||
struct UnaryOperationWrapper : BinaryOperationBase
|
||||
{
|
||||
Operation &op;
|
||||
|
||||
|
|
@ -113,7 +113,7 @@ void test_unary_operation(Operation &op)
|
|||
test_binary_operation(wrapped);
|
||||
}
|
||||
|
||||
struct ShlTest : BinaryOperationBase
|
||||
struct ShlTest : BinaryOperationBase
|
||||
{
|
||||
ShlTest()
|
||||
{
|
||||
|
|
@ -138,7 +138,7 @@ struct ShlTest : BinaryOperationBase
|
|||
}
|
||||
} shl;
|
||||
|
||||
struct ShrTest : BinaryOperationBase
|
||||
struct ShrTest : BinaryOperationBase
|
||||
{
|
||||
ShrTest()
|
||||
{
|
||||
|
|
@ -163,7 +163,7 @@ struct ShrTest : BinaryOperationBase
|
|||
}
|
||||
} shr;
|
||||
|
||||
struct SshrTest : BinaryOperationBase
|
||||
struct SshrTest : BinaryOperationBase
|
||||
{
|
||||
SshrTest()
|
||||
{
|
||||
|
|
@ -189,7 +189,7 @@ struct SshrTest : BinaryOperationBase
|
|||
}
|
||||
} sshr;
|
||||
|
||||
struct AddTest : BinaryOperationBase
|
||||
struct AddTest : BinaryOperationBase
|
||||
{
|
||||
AddTest()
|
||||
{
|
||||
|
|
@ -209,7 +209,7 @@ struct AddTest : BinaryOperationBase
|
|||
}
|
||||
} add;
|
||||
|
||||
struct SubTest : BinaryOperationBase
|
||||
struct SubTest : BinaryOperationBase
|
||||
{
|
||||
SubTest()
|
||||
{
|
||||
|
|
|
|||
|
|
@ -6,12 +6,12 @@ Pytest options you might want:
|
|||
|
||||
- `-v`: More progress indication.
|
||||
|
||||
- `--basetemp tmp`: Store test files (including vcd results) in tmp.
|
||||
- `--basetemp tmp`: Store test files (including vcd results) in tmp.
|
||||
CAREFUL: contents of tmp will be deleted
|
||||
|
||||
- `-k <pattern>`: Run only tests that contain the pattern, e.g.
|
||||
`-k cxx` or `-k smt` or `-k demux` or `-k 'cxx[demux`
|
||||
|
||||
|
||||
- `-s`: Don't hide stdout/stderr from the test code.
|
||||
|
||||
Custom options for functional backend tests:
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue