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Merge branch 'main' into nella/latch-toggle

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nella 2026-07-08 11:41:08 +02:00 • committed by GitHub
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1
tests/Makefile
View file

@ -75,6 +75,7 @@ MK_TEST_DIRS += ./memories
MK_TEST_DIRS += ./aiger
MK_TEST_DIRS += ./alumacc
MK_TEST_DIRS += ./check_mem
MK_TEST_DIRS += ./write_verilog
all: vanilla-test

1
tests/arch/analogdevices/asym_ram_sdp.ys
View file

@ -47,4 +47,3 @@ chparam -set SIZEA 768
chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
select -assert-count 2 t:RBRAM2

2
tests/arch/analogdevices/asym_ram_sdp_read_wider.v
View file

@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;

8
tests/arch/analogdevices/attributes_test.ys
View file

@ -4,7 +4,7 @@ hierarchy -top block_ram
synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
# select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive.
# Check that distributed memory without parameters is not modified
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -13,7 +13,7 @@ synth_analogdevices -top distributed_ram -noiopad
cd distributed_ram # Constrain all select calls below inside the top module
select -assert-count 8 t:RAMS64X1
select -assert-count 8 t:FFRE
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -22,7 +22,7 @@ synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 64 t:RAMS64X1
select -assert-count 4 t:FFRE
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -30,7 +30,7 @@ setattr -set logic_block 1 block_ram/m:*
synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 0 t:RBRAM2
# Set ram_style block to a distributed memory; will be implemented as blockram
design -reset
read_verilog ../common/memory_attributes/attributes_test.v

4
tests/arch/analogdevices/blockram.ys
View file

@ -54,7 +54,7 @@ select -assert-count 1 t:RBRAM2
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp
@ -62,7 +62,7 @@ select -assert-count 1 t:RBRAM2
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set logic_block 1 m:memory
synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp

6
tests/arch/analogdevices/bug1598.ys
View file

@ -3,14 +3,14 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices

1
tests/arch/analogdevices/dffs.ys
View file

@ -38,4 +38,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:FFRE
select -assert-none t:FFRE %% t:* %D

5
tests/arch/analogdevices/dsp_abc9.ys
View file

@ -17,7 +17,7 @@ module top(input signed [24:0] A, input signed [17:0] B, output [47:0] P);
assign P = A * B;
endmodule
EOT
synth_analogdevices
synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
opt -full -fine
select -assert-count 2 t:$mul
@ -34,9 +34,8 @@ EOT
async2sync
techmap -map +/analogdevices/dsp_map.v
verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
synth_analogdevices
synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
opt -full -fine
select -assert-count 0 t:* t:$assert %d
sat -verify -prove-asserts

3
tests/arch/common/blockram.v
View file

@ -233,7 +233,7 @@ endmodule // double_sync_ram_sdp
module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
(input wire clk_a, clk_b,
(input wire clk_a, clk_b,
input wire write_enable_a, write_enable_b,
input wire read_enable_a, read_enable_b,
input wire [DATA_WIDTH-1:0] write_data_a, write_data_b,
@ -325,4 +325,3 @@ module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
);
endmodule // double_sync_ram_tdp

2
tests/arch/common/fsm.v
View file

@ -19,7 +19,7 @@
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end
end
else
case(state)
IDLE : if (req_0 == 1'b1) begin

1
tests/arch/common/memory_attributes/attributes_test.v
View file

@ -85,4 +85,3 @@ module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
assign data_out = data_out_r;
endmodule // distributed_ram

2
tests/arch/common/shifter.v
View file

@ -13,5 +13,5 @@ module top(out, clk, in);
begin
out <= out >> 1;
out[7] <= in;
end
end
endmodule

1
tests/arch/ecp5/add_sub.ys
View file

@ -9,4 +9,3 @@ select -assert-max 26 t:LUT4
select -assert-count 10 t:PFUMX
select -assert-count 6 t:L6MUX21
select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D

4
tests/arch/ecp5/bug1598.ys
View file

@ -3,13 +3,13 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc

64
tests/arch/ecp5/bug1836.mem
View file

@ -1,32 +1,32 @@
0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1,
0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10,
0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a,
0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842,
0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6,
0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504,
0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3,
0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5,
0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d,
0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b,
0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23,
0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3,
0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3,
0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de,
0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b,
0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324,
0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e,
0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef,
0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85,
0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd,
0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759,
0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb,
0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c,
0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa,
0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2,
0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894,
0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc,
0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c,
0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c,
0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21,
0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4,
0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb,
0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1,
0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10,
0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a,
0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842,
0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6,
0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504,
0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3,
0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5,
0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d,
0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b,
0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23,
0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3,
0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3,
0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de,
0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b,
0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324,
0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e,
0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef,
0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85,
0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd,
0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759,
0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb,
0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c,
0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa,
0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2,
0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894,
0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc,
0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c,
0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c,
0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21,
0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4,
0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb,

2
tests/arch/ecp5/dffs.ys
View file

@ -16,4 +16,4 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
select -assert-none t:TRELLIS_FF %% t:* %D

2
tests/arch/ecp5/memories.ys
View file

@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp
hierarchy -top sync_ram_tdp
synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp
select -assert-count 1 t:DP16KD
select -assert-count 1 t:DP16KD
select -assert-none t:LUT4

2
tests/arch/ecp5/shifter.ys
View file

@ -5,6 +5,6 @@ flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D

1
tests/arch/efinix/add_sub.ys
View file

@ -7,4 +7,3 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:EFX_ADD
select -assert-count 4 t:EFX_LUT4
select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D

64
tests/arch/fabulous/arith_map.v Normal file
View file

@ -0,0 +1,64 @@
`default_nettype none
`ifdef ARITH_ha
(* techmap_celltype = "$alu" *)
module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] CARRY;
LUT4_HA #(
.INIT(16'b0),
.I0MUX(1'b1)
) carry_start (
.I0(), .I1(CI), .I2(CI), .I3(),
.Ci(),
.Co(CARRY[0])
);
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
LUT4_HA #(
.INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0)
.I0MUX(1'b1)
) lut_i (
.I0(), .I1(AA[i]), .I2(BB[i]), .I3(),
.Ci(CARRY[i]),
.O(Y[i]),
.Co(CARRY[i+1])
);
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
`endif

2
tests/arch/fabulous/carry.ys
View file

@ -1,7 +1,7 @@
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -carry ha # equivalency check
equiv_opt -assert -map prims.v synth_fabulous -carry ha -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-max 10 t:LUT4_HA

30
tests/arch/fabulous/cells_map.v Normal file
View file

@ -0,0 +1,30 @@
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else
if (WIDTH == 5) begin
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .I5(A[5]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule

2
tests/arch/fabulous/complexflop.ys
View file

@ -25,7 +25,7 @@ EOT
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -complex-dff # equivalency check
equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DFFE_PP_ x -ff $_SDFF_PP?_ x -ff $_SDFFCE_PP?P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -extra-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

2
tests/arch/fabulous/counter.ys
View file

@ -15,7 +15,7 @@ EOT
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check
equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

9
tests/arch/fabulous/ff_map.v Normal file
View file

@ -0,0 +1,9 @@
module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); LUTFF_E _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E)); endmodule
module \$_SDFF_PP0_ (input D, C, R, output Q); LUTFF_SR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .R(R)); endmodule
module \$_SDFF_PP1_ (input D, C, R, output Q); LUTFF_SS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .S(R)); endmodule
module \$_SDFFCE_PP0P_ (input D, C, E, R, output Q); LUTFF_ESR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .R(R)); endmodule
module \$_SDFFCE_PP1P_ (input D, C, E, R, output Q); LUTFF_ESS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .S(R)); endmodule

2
tests/arch/fabulous/fsm.ys
View file

@ -3,7 +3,7 @@ hierarchy -top fsm
proc
flatten
equiv_opt -run :prove -map +/fabulous/prims.v synth_fabulous
equiv_opt -run :prove -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v
async2sync
miter -equiv -make_assert -flatten gold gate miter
stat

15
tests/arch/fabulous/io_map.v Normal file
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@ -0,0 +1,15 @@
module \$__FABULOUS_IBUF (input PAD, output OUT);
IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(1'b1), .O(OUT), .PAD(PAD));
endmodule
module \$__FABULOUS_OBUF (output PAD, input IN);
IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(1'b0), .I(IN), .PAD(PAD));
endmodule
module \$__FABULOUS_TBUF (output PAD, output IN, output EN);
IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(!EN), .I(IN), .PAD(PAD));
endmodule
module \$__FABULOUS_IOBUF (inout PAD, output OUT, input IN, output EN);
IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(!EN), .I(IN), .O(OUT), .PAD(PAD));
endmodule

11
tests/arch/fabulous/latches_map.v Normal file
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@ -0,0 +1,11 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

2
tests/arch/fabulous/logic.ys
View file

@ -1,7 +1,7 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check
equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-max 1 t:LUT1

488
tests/arch/fabulous/prims.v Normal file
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@ -0,0 +1,488 @@
module LUT1(output O, input I0);
parameter [1:0] INIT = 0;
assign O = I0 ? INIT[1] : INIT[0];
endmodule
module LUT2(output O, input I0, I1);
parameter [3:0] INIT = 0;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT3(output O, input I0, I1, I2);
parameter [7:0] INIT = 0;
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
parameter [15:0] INIT = 0;
parameter I0MUX = 1'b1;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
wire I0_sel = I0MUX ? Ci : I0;
assign O = I0_sel ? s1[1] : s1[0];
assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
endmodule
module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0;
wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT55_FCY (output O, Co, input I0, I1, I2, I3, I4, Ci);
parameter [63:0] INIT = 0;
wire comb1, comb2;
LUT5 #(.INIT(INIT[31: 0])) l5_1 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb1));
LUT5 #(.INIT(INIT[63:32])) l5_2 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb2));
assign O = comb1 ^ Ci;
assign Co = comb1 ? Ci : comb2;
endmodule
module LUTFF(input CLK, D, output reg O);
initial O = 1'b0;
always @ (posedge CLK) begin
O <= D;
end
endmodule
module FABULOUS_MUX2(input I0, I1, S0, output O);
assign O = S0 ? I1 : I0;
endmodule
module FABULOUS_MUX4(input I0, I1, I2, I3, S0, S1, output O);
wire A0 = S0 ? I1 : I0;
wire A1 = S0 ? I3 : I2;
assign O = S1 ? A1 : A0;
endmodule
module FABULOUS_MUX8(input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, output O);
wire A0 = S0 ? I1 : I0;
wire A1 = S0 ? I3 : I2;
wire A2 = S0 ? I5 : I4;
wire A3 = S0 ? I7 : I6;
wire B0 = S1 ? A1 : A0;
wire B1 = S1 ? A3 : A2;
assign O = S2 ? B1 : B0;
endmodule
module FABULOUS_LC #(
parameter K = 4,
parameter [2**K-1:0] INIT = 0,
parameter DFF_ENABLE = 1'b0
) (
input CLK,
input [K-1:0] I,
output O,
output Q
);
wire f_wire;
//LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
generate
if (K == 1) begin
LUT1 #(.INIT(INIT)) lut1 (.O(f_wire), .I0(I[0]));
end else
if (K == 2) begin
LUT2 #(.INIT(INIT)) lut2 (.O(f_wire), .I0(I[0]), .I1(I[1]));
end else
if (K == 3) begin
LUT3 #(.INIT(INIT)) lut3 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]));
end else
if (K == 4) begin
LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]));
end
endgenerate
LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
assign O = f_wire;
endmodule
(* blackbox *)
module Global_Clock (output CLK);
`ifndef SYNTHESIS
initial CLK = 0;
always #10 CLK = ~CLK;
`endif
endmodule
(* blackbox, keep *)
module InPass4_frame_config (input CLK, output O0, O1, O2, O3);
endmodule
(* blackbox, keep *)
module OutPass4_frame_config (input CLK, I0, I1, I2, I3);
endmodule
(* blackbox, keep *)
module InPass4_frame_config_mux #(
parameter [3:0] O_reg = 0
) (
input CLK,
output O0,
output O1,
output O2,
output O3
);
endmodule
(* blackbox, keep *)
module OutPass4_frame_config_mux #(
parameter [3:0] I_reg = 0
) (
input I0,
input I1,
input I2,
input I3,
input CLK
);
endmodule
(* keep *)
module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD);
assign PAD = T ? 1'bz : I;
assign O = PAD;
reg Q_q;
always @(posedge CLK) Q_q <= O;
assign Q = Q_q;
endmodule
module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, CLK);
parameter A_reg = 1'b0;
parameter B_reg = 1'b0;
parameter C_reg = 1'b0;
parameter ACC = 1'b0;
parameter signExtension = 1'b0;
parameter ACCout = 1'b0;
//parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value)
// IMPORTANT: this has to be in a dedicated line
input A7;// operand A
input A6;
input A5;
input A4;
input A3;
input A2;
input A1;
input A0;
input B7;// operand B
input B6;
input B5;
input B4;
input B3;
input B2;
input B1;
input B0;
input C19;// operand C
input C18;
input C17;
input C16;
input C15;
input C14;
input C13;
input C12;
input C11;
input C10;
input C9;
input C8;
input C7;
input C6;
input C5;
input C4;
input C3;
input C2;
input C1;
input C0;
output Q19;// result
output Q18;
output Q17;
output Q16;
output Q15;
output Q14;
output Q13;
output Q12;
output Q11;
output Q10;
output Q9;
output Q8;
output Q7;
output Q6;
output Q5;
output Q4;
output Q3;
output Q2;
output Q1;
output Q0;
input clr;
input CLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
wire [7:0] A; // port A read data
wire [7:0] B; // port B read data
wire [19:0] C; // port B read data
reg [7:0] A_q; // port A read data register
reg [7:0] B_q; // port B read data register
reg [19:0] C_q; // port B read data register
wire [7:0] OPA; // port A
wire [7:0] OPB; // port B
wire [19:0] OPC; // port B
reg [19:0] ACC_data ; // accumulator register
wire [19:0] sum;// port B read data register
wire [19:0] sum_in;// port B read data register
wire [15:0] product;
wire [19:0] product_extended;
assign A = {A7,A6,A5,A4,A3,A2,A1,A0};
assign B = {B7,B6,B5,B4,B3,B2,B1,B0};
assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0};
assign OPA = A_reg ? A_q : A;
assign OPB = B_reg ? B_q : B;
assign OPC = C_reg ? C_q : C;
assign sum_in = ACC ? ACC_data : OPC;// we can
assign product = OPA * OPB;
// The sign extension was not tested
assign product_extended = signExtension ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product};
assign sum = product_extended + sum_in;
assign Q19 = ACCout ? ACC_data[19] : sum[19];
assign Q18 = ACCout ? ACC_data[18] : sum[18];
assign Q17 = ACCout ? ACC_data[17] : sum[17];
assign Q16 = ACCout ? ACC_data[16] : sum[16];
assign Q15 = ACCout ? ACC_data[15] : sum[15];
assign Q14 = ACCout ? ACC_data[14] : sum[14];
assign Q13 = ACCout ? ACC_data[13] : sum[13];
assign Q12 = ACCout ? ACC_data[12] : sum[12];
assign Q11 = ACCout ? ACC_data[11] : sum[11];
assign Q10 = ACCout ? ACC_data[10] : sum[10];
assign Q9 = ACCout ? ACC_data[9] : sum[9];
assign Q8 = ACCout ? ACC_data[8] : sum[8];
assign Q7 = ACCout ? ACC_data[7] : sum[7];
assign Q6 = ACCout ? ACC_data[6] : sum[6];
assign Q5 = ACCout ? ACC_data[5] : sum[5];
assign Q4 = ACCout ? ACC_data[4] : sum[4];
assign Q3 = ACCout ? ACC_data[3] : sum[3];
assign Q2 = ACCout ? ACC_data[2] : sum[2];
assign Q1 = ACCout ? ACC_data[1] : sum[1];
assign Q0 = ACCout ? ACC_data[0] : sum[0];
always @ (posedge CLK)
begin
A_q <= A;
B_q <= B;
C_q <= C;
if (clr == 1'b1) begin
ACC_data <= 20'b00000000000000000000;
end else begin
ACC_data <= sum;
end
end
endmodule
module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, CLK);
//parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value)
parameter AD_reg = 1'b0;
parameter BD_reg = 1'b0;
// IMPORTANT: this has to be in a dedicated line
input D0; // Register File write port
input D1;
input D2;
input D3;
input W_ADR0;
input W_ADR1;
input W_ADR2;
input W_ADR3;
input W_ADR4;
input W_en;
output AD0;// Register File read port A
output AD1;
output AD2;
output AD3;
input A_ADR0;
input A_ADR1;
input A_ADR2;
input A_ADR3;
input A_ADR4;
output BD0;//Register File read port B
output BD1;
output BD2;
output BD3;
input B_ADR0;
input B_ADR1;
input B_ADR2;
input B_ADR3;
input B_ADR4;
input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
//type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit
//signal mem : memtype := (others => (others => '0'));
reg [3:0] mem [31:0];
wire [4:0] W_ADR;// write address
wire [4:0] A_ADR;// port A read address
wire [4:0] B_ADR;// port B read address
wire [3:0] D; // write data
wire [3:0] AD; // port A read data
wire [3:0] BD; // port B read data
reg [3:0] AD_q; // port A read data register
reg [3:0] BD_q; // port B read data register
integer i;
assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0};
assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0};
assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0};
assign D = {D3,D2,D1,D0};
initial begin
for (i=0; i<32; i=i+1) begin
mem[i] = 4'b0000;
end
end
always @ (posedge CLK) begin : P_write
if (W_en == 1'b1) begin
mem[W_ADR] <= D ;
end
end
assign AD = mem[A_ADR];
assign BD = mem[B_ADR];
always @ (posedge CLK) begin
AD_q <= AD;
BD_q <= BD;
end
assign AD0 = AD_reg ? AD_q[0] : AD[0];
assign AD1 = AD_reg ? AD_q[1] : AD[1];
assign AD2 = AD_reg ? AD_q[2] : AD[2];
assign AD3 = AD_reg ? AD_q[3] : AD[3];
assign BD0 = BD_reg ? BD_q[0] : BD[0];
assign BD1 = BD_reg ? BD_q[1] : BD[1];
assign BD2 = BD_reg ? BD_q[2] : BD[2];
assign BD3 = BD_reg ? BD_q[3] : BD[3];
endmodule
module LUTFF(input CLK, D, output reg O);
initial O = 1'b0;
always @ (posedge CLK) begin
O <= D;
end
endmodule
module LUTFF_E (
output reg O,
input CLK, E, D
);
initial O = 1'b0;
always @(posedge CLK)
if (E)
O <= D;
endmodule
module LUTFF_SR (
output reg O,
input CLK, R, D
);
initial O = 1'b0;
always @(posedge CLK)
if (R)
O <= 0;
else
O <= D;
endmodule
module LUTFF_SS (
output reg O,
input CLK, S, D
);
initial O = 1'b0;
always @(posedge CLK)
if (S)
O <= 1;
else
O <= D;
endmodule
module LUTFF_ESR (
output reg O,
input CLK, E, R, D
);
initial O = 1'b0;
always @(posedge CLK)
if (E) begin
if (R)
O <= 0;
else
O <= D;
end
endmodule
module LUTFF_ESS (
output reg O,
input CLK, E, S, D
);
initial O = 1'b0;
always @(posedge CLK)
if (E) begin
if (S)
O <= 1;
else
O <= D;
end
endmodule

46
tests/arch/fabulous/ram_regfile.txt Normal file
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@ -0,0 +1,46 @@
# Yosys doesn't support configurable sync/async ports.
# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync
ram distributed $__REGFILE_AA_ {
abits 5;
width 4;
cost 6;
port sw "W" {
clock posedge "CLK";
}
port ar "A" {
}
port ar "B" {
}
}
ram distributed $__REGFILE_SA_ {
abits 5;
width 4;
cost 5;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port ar "B" {
}
}
ram distributed $__REGFILE_SS_ {
abits 5;
width 4;
cost 4;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port sr "B" {
clock posedge "CLK";
}
}

2
tests/arch/fabulous/regfile.ys
View file

@ -10,7 +10,7 @@ module sync_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output r
endmodule
EOT
synth_fabulous -top sync_sync
synth_fabulous -top sync_sync -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -arith-map arith_map.v -cells-map cells_map.v -extra-map ff_map.v -extra-map latches_map.v -extra-mlibmap ram_regfile.txt -extra-map regfile_map.v
cd sync_sync
select -assert-count 1 t:RegFile_32x4

42
tests/arch/fabulous/regfile_map.v Normal file
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@ -0,0 +1,42 @@
(* techmap_celltype = "$__REGFILE_[AS][AS]_" *)
module \$__REGFILE_XX_ (...);
parameter _TECHMAP_CELLTYPE_ = "";
localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S";
localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S";
localparam WIDTH = 4;
localparam ABITS = 5;
input [WIDTH-1:0] PORT_W_WR_DATA;
input [ABITS-1:0] PORT_W_ADDR;
input PORT_W_WR_EN;
output [WIDTH-1:0] PORT_A_RD_DATA;
input [ABITS-1:0] PORT_A_ADDR;
output [WIDTH-1:0] PORT_B_RD_DATA;
input [ABITS-1:0] PORT_B_ADDR;
// Unused - we have a shared clock - but keep techmap happy
input PORT_W_CLK;
input PORT_A_CLK;
input PORT_B_CLK;
input CLK_CLK;
RegFile_32x4 #(
.AD_reg(A_SYNC),
.BD_reg(B_SYNC)
) _TECHMAP_REPLACE_ (
.D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]),
.W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]),
.W_en(PORT_W_WR_EN),
.AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]),
.A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]),
.BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]),
.B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]),
.CLK(CLK_CLK)
);
endmodule

2
tests/arch/fabulous/tribuf.ys
View file

@ -4,7 +4,7 @@ proc
tribuf
flatten
synth
equiv_opt -assert -map +/fabulous/prims.v -map +/simcells.v synth_fabulous -iopad # equivalency check
equiv_opt -assert -map prims.v -map +/simcells.v synth_fabulous -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v -extra-map io_map.v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
select -assert-count 3 t:IO_1_bidirectional_frame_config_pass

1
tests/arch/gowin/add_sub.ys
View file

@ -10,4 +10,3 @@ select -assert-count 8 t:IBUF
select -assert-count 1 t:GND
select -assert-count 1 t:VCC
select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D

2
tests/arch/gowin/compare.ys
View file

@ -5,5 +5,3 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 5 t:ALU

2
tests/arch/gowin/tribuf.ys
View file

@ -11,4 +11,4 @@ cd tristate # Constrain all select calls below inside the top module
select -assert-count 1 t:TBUF
select -assert-count 1 t:LUT1
select -assert-count 2 t:IBUF
select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D

1
tests/arch/ice40/add_sub.ys
View file

@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:SB_LUT4
select -assert-count 6 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D

4
tests/arch/ice40/bug1598.ys
View file

@ -3,13 +3,13 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc

8
tests/arch/ice40/bug1626.ys
View file

@ -182,20 +182,20 @@ module \ahb_async_sram_halfwidth
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
case 1'1
case
case
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
switch \ahbls_hready
case 1'1
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
switch \ahbls_htrans [1]
case 1'1
case
case
end
case
case
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
case 1'1
case
case
end
end
end

2
tests/arch/ice40/dffs.ys
View file

@ -16,4 +16,4 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
select -assert-none t:SB_DFFE %% t:* %D

6
tests/arch/ice40/ice40_dsp_const.ys
View file

@ -75,7 +75,7 @@ EOT
techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
async2sync
equiv_make top ref equiv
select -assert-any -module equiv t:$equiv
equiv_induct
equiv_make top ref equiv
select -assert-any -module equiv t:$equiv
equiv_induct
equiv_status -assert

2
tests/arch/ice40/spram.v
View file

@ -6,7 +6,7 @@ parameter SKIP_RDEN = 1;
input clk;
input write_enable, read_enable;
input [DATA_WIDTH - 1 : 0] write_data;
input [ADDR_WIDTH - 1 : 0] addr;
input [ADDR_WIDTH - 1 : 0] addr;
output [DATA_WIDTH - 1 : 0] read_data;
(* ram_style = "huge" *)

1
tests/arch/intel_alm/add_sub.ys
View file

@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
stat
select -assert-count 9 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D

1
tests/arch/intel_alm/adffs.ys
View file

@ -45,4 +45,3 @@ select -assert-count 1 t:MISTRAL_FF
select -assert-count 2 t:MISTRAL_NOT
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D

1
tests/arch/intel_alm/blockram.ys
View file

@ -5,4 +5,3 @@ cd sync_ram_sdp
select -assert-count 1 t:MISTRAL_NOT
select -assert-count 1 t:MISTRAL_M10K
select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D

1
tests/arch/intel_alm/counter.ys
View file

@ -10,4 +10,3 @@ select -assert-count 2 t:MISTRAL_NOT
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D

1
tests/arch/intel_alm/dffs.ys
View file

@ -18,4 +18,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D

1
tests/arch/intel_alm/fsm.ys
View file

@ -19,4 +19,3 @@ select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D

1
tests/arch/intel_alm/logic.ys
View file

@ -9,4 +9,3 @@ select -assert-count 1 t:MISTRAL_NOT
select -assert-count 6 t:MISTRAL_ALUT2
select -assert-count 2 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D

1
tests/arch/intel_alm/lutram.ys
View file

@ -37,4 +37,3 @@ select -assert-count 2 t:MISTRAL_ALUT2
select -assert-count 8 t:MISTRAL_ALUT3
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D

1
tests/arch/intel_alm/mul.ys
View file

@ -32,4 +32,3 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_MUL27X27
select -assert-none t:MISTRAL_MUL27X27 %% t:* %D

1
tests/arch/intel_alm/mux.ys
View file

@ -42,4 +42,3 @@ select -assert-max 1 t:MISTRAL_ALUT3
select -assert-max 2 t:MISTRAL_ALUT5
select -assert-max 5 t:MISTRAL_ALUT6
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D

1
tests/arch/intel_alm/shifter.ys
View file

@ -7,4 +7,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_FF %% t:* %D

1
tests/arch/intel_alm/tribuf.ys
View file

@ -10,4 +10,3 @@ cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it.
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D

1
tests/arch/microchip/.gitignore vendored
View file

@ -1,2 +1 @@
*.vm

8
tests/arch/microchip/dff.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -73,4 +73,4 @@ synth_microchip -top dffs -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-count 1 t:CFG1
select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D

8
tests/arch/microchip/dff_opt.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -39,4 +39,4 @@ synth_microchip -top dff_opt -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CFG4
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D
select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D

8
tests/arch/microchip/dsp.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -120,7 +120,7 @@ output reg cout;
input [n:0] a;
input [n:0] b;
input [n-1:0] c;
always @(*)
always @(*)
begin
{cout,out} = a * b + c;
end

6
tests/arch/microchip/mult.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

10
tests/arch/microchip/ram_SDP.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -27,7 +27,7 @@ output reg [d_width-1:0] q;
reg [d_width-1:0] mem [mem_depth-1:0];
always @(posedge clk) begin
if (we) begin
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];
@ -47,4 +47,4 @@ hierarchy -top sync_ram_sdp
chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
synth_microchip -top sync_ram_sdp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D
select -assert-none t:RAM1K20 %% t:* %D

10
tests/arch/microchip/ram_TDP.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -28,7 +28,7 @@ reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
always @ (posedge clka)
begin
addra_reg <= addra;
if(wea) begin
mem[addra] <= dataina;
qa <= dataina;
@ -61,4 +61,4 @@ chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
synth_microchip -top sync_ram_tdp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-count 2 t:CFG1
select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
select -assert-none t:RAM1K20 t:CFG1 %% t:* %D

7
tests/arch/microchip/reduce.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -25,4 +25,3 @@ EOT
synth_microchip -top reduce -family polarfire -noiopad
select -assert-count 1 t:XOR8
select -assert-none t:XOR8 %% t:* %D

8
tests/arch/microchip/simple_ram.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -19,4 +19,4 @@ hierarchy -top sync_ram_sp
chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
synth_microchip -top sync_ram_sp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D
select -assert-none t:RAM1K20 %% t:* %D

8
tests/arch/microchip/uram_ar.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -28,7 +28,7 @@ reg [d_width-1:0] mem [mem_depth-1:0];
assign q = mem[waddr];
always @(posedge clk) begin
if (we)
if (we)
mem[waddr] <= data;
end

8
tests/arch/microchip/uram_sr.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -32,7 +32,7 @@ module uram_sr(clk, wr, raddr, din, waddr, dout);
end
always@(posedge clk) begin
raddr_reg <= raddr;
raddr_reg <= raddr;
if(wr)
mem[waddr]<= din;
end

8
tests/arch/microchip/widemux.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -38,4 +38,4 @@ equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:CFG3
select -assert-none t:CFG3 %% t:* %D
select -assert-none t:CFG3 %% t:* %D

2
tests/arch/nanoxplore/meminit.v
View file

@ -31,7 +31,7 @@ always @(posedge clk) begin
read_addr <= counter;
read_val <= mem[counter];
end else begin
did_read <= 1'b0;
did_read <= 1'b0;
end
if (!done)

6
tests/arch/nanoxplore/meminit.ys
View file

@ -3,7 +3,7 @@ chparam -set DEPTH_LOG2 5 -set WIDTH 36
prep
opt_dff
prep -rdff
synth_nanoxplore
synth_nanoxplore
clean_zerowidth
select -assert-none t:$mem_v2 t:$mem
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@ -18,7 +18,7 @@ chparam -set DEPTH_LOG2 6 -set WIDTH 18
prep
opt_dff
prep -rdff
synth_nanoxplore
synth_nanoxplore
clean_zerowidth
select -assert-none t:$mem_v2 t:$mem
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@ -34,7 +34,7 @@ chparam -set DEPTH_LOG2 8 -set WIDTH 18
prep
opt_dff
prep -rdff
synth_nanoxplore
synth_nanoxplore
clean_zerowidth
select -assert-none t:$mem_v2 t:$mem
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v

4
tests/arch/quicklogic/qlf_k6n10f/dffs.ys
View file

@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dff # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre
select -assert-none t:sdffsre %% t:* %D
select -assert-none t:sdffsre %% t:* %D
design -load read
hierarchy -top my_dffe
@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre
select -assert-none t:sdffsre %% t:* %D
select -assert-none t:sdffsre %% t:* %D

4
tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
View file

@ -46,7 +46,7 @@ initial begin
end
`MEM_TEST_VECTOR
end
@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
always @(posedge clk) begin
if (i < VECTORLEN-1) begin
if (i > 0) begin
if($past(rce_a))
if($past(rce_a))
assert(rq_a == rq_a_e);
if($past(rce_b))
assert(rq_b == rq_b_e);

2
tests/arch/quicklogic/qlf_k6n10f/meminit.v
View file

@ -31,7 +31,7 @@ always @(posedge clk) begin
read_addr <= counter;
read_val <= mem[counter];
end else begin
did_read <= 1'b0;
did_read <= 1'b0;
end
if (!done)

1
tests/arch/xilinx/asym_ram_sdp.ys
View file

@ -47,4 +47,3 @@ chparam -set SIZEA 768
chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
synth_xilinx -top asym_ram_sdp_read_wider -noiopad
select -assert-count 1 t:RAMB18E1

4
tests/arch/xilinx/asym_ram_sdp_read_wider.v
View file

@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
@ -69,4 +69,4 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
end
end
assign doB = readB;
endmodule
endmodule

2
tests/arch/xilinx/asym_ram_sdp_write_wider.v
View file

@ -68,4 +68,4 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
end
end
end
endmodule
endmodule

8
tests/arch/xilinx/attributes_test.ys
View file

@ -4,7 +4,7 @@ hierarchy -top block_ram
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1
# Check that distributed memory without parameters is not modified
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -12,7 +12,7 @@ hierarchy -top distributed_ram
synth_xilinx -top distributed_ram -noiopad
cd distributed_ram # Constrain all select calls below inside the top module
select -assert-count 1 t:RAM32M
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -20,7 +20,7 @@ setattr -set ram_style "distributed" block_ram/m:*
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 16 t:RAM256X1S
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -28,7 +28,7 @@ setattr -set logic_block 1 block_ram/m:*
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 0 t:RAMB18E1
# Set ram_style block to a distributed memory; will be implemented as blockram
design -reset
read_verilog ../common/memory_attributes/attributes_test.v

4
tests/arch/xilinx/blockram.ys
View file

@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
synth_xilinx -top sync_ram_sdp -noiopad
cd sync_ram_sdp
@ -58,7 +58,7 @@ select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set logic_block 1 m:memory
synth_xilinx -top sync_ram_sdp -noiopad
cd sync_ram_sdp

4
tests/arch/xilinx/bug1598.ys
View file

@ -3,13 +3,13 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc

1
tests/arch/xilinx/dffs.ys
View file

@ -42,4 +42,3 @@ cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D

1
tests/arch/xilinx/dsp_cascade.ys
View file

@ -87,4 +87,3 @@ select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
# (see above for explanation)
select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i

19
tests/arch/xilinx/dynamic_upto_select.ys Normal file
View file

@ -0,0 +1,19 @@
# https://github.com/YosysHQ/yosys/issues/892
read_verilog <<EOT
module top (input clk, sel, di, output do);
reg [0:1] data [0:0];
always @(posedge clk)
data[0] <= {di, data[0][0]};
assign do = data[0][sel];
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
design -load postopt
select -assert-count 1 t:BUFG
select -assert-count 2 t:FDRE
select -assert-count 1 t:LUT3
select -assert-none t:BUFG t:FDRE t:LUT3 %% t:* %D

2
tests/arch/xilinx/xilinx_srl.v
View file

@ -34,7 +34,7 @@ parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
if (E)
if (E)
r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule

2
tests/arith_tree/arith_tree_alu_macc_equiv.ys
View file

@ -104,4 +104,4 @@ equiv_opt -assert arith_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
design -reset

1
tests/arith_tree/arith_tree_final_adder.ys
View file

@ -67,4 +67,3 @@ select -assert-none t:$add
select -assert-min 1 t:$_AND_
select -assert-min 1 t:$_XOR_
design -reset

10
tests/asicworld/code_hdl_models_GrayCounter.v
View file

@ -6,19 +6,19 @@
module GrayCounter
#(parameter COUNTER_WIDTH = 4)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
@ -29,5 +29,5 @@ module GrayCounter
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule

60
tests/asicworld/code_hdl_models_arbiter.v
View file

@ -3,32 +3,32 @@
// orginally coded by WD Peterson in VHDL.
//----------------------------------------------------
module arbiter (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
// --------------Port Declaration-----------------------
input clk;
input rst;
input req3;
input req2;
input req1;
input req0;
output gnt3;
output gnt2;
output gnt1;
output gnt0;
// --------------Port Declaration-----------------------
input clk;
input rst;
input req3;
input req2;
input req1;
input req0;
output gnt3;
output gnt2;
output gnt1;
output gnt0;
//--------------Internal Registers----------------------
wire [1:0] gnt ;
wire comreq ;
wire [1:0] gnt ;
wire comreq ;
wire beg ;
wire [1:0] lgnt ;
wire lcomreq ;
@ -41,14 +41,14 @@ reg lmask0 ;
reg lmask1 ;
reg ledge ;
//--------------Code Starts Here-----------------------
//--------------Code Starts Here-----------------------
always @ (posedge clk)
if (rst) begin
lgnt0 <= 0;
lgnt1 <= 0;
lgnt2 <= 0;
lgnt3 <= 0;
end else begin
end else begin
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
@ -69,18 +69,18 @@ end else begin
| (~lcomreq & lmask1 & ~lmask0 & req3)
| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
| ( lcomreq & lgnt3);
end
end
//----------------------------------------------------
// lasmask state machine.
//----------------------------------------------------
assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
always @ (posedge clk)
begin
begin
lasmask <= (beg & ~ledge & ~lasmask);
ledge <= (beg & ~ledge & lasmask)
ledge <= (beg & ~ledge & lasmask)
| (beg & ledge & ~lasmask);
end
end
//----------------------------------------------------
// comreq logic.
@ -108,7 +108,7 @@ end else if(lasmask) begin
end else begin
lmask1 <= lmask1;
lmask0 <= lmask0;
end
end
assign comreq = lcomreq;
assign gnt = lgnt;

30
tests/asicworld/code_hdl_models_arbiter_tb.v
View file

@ -6,10 +6,10 @@ reg req3 = 0;
reg req2 = 0;
reg req1 = 0;
reg req0 = 0;
wire gnt3;
wire gnt2;
wire gnt1;
wire gnt0;
wire gnt3;
wire gnt2;
wire gnt1;
wire gnt0;
// Clock generator
always #1 clk = ~clk;
@ -41,20 +41,20 @@ initial begin
req0 <= 0;
repeat (1) @ (posedge clk);
#10 $finish;
end
end
// Connect the DUT
arbiter U (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
endmodule

16
tests/asicworld/code_hdl_models_cam.v
View file

@ -9,18 +9,18 @@ clk , // Cam clock
cam_enable , // Cam enable
cam_data_in , // Cam data to match
cam_hit_out , // Cam match has happened
cam_addr_out // Cam output address
cam_addr_out // Cam output address
);
parameter ADDR_WIDTH = 8;
parameter DEPTH = 1 << ADDR_WIDTH;
//------------Input Ports--------------
input clk;
input cam_enable;
input [DEPTH-1:0] cam_data_in;
input clk;
input cam_enable;
input [DEPTH-1:0] cam_data_in;
//----------Output Ports--------------
output cam_hit_out;
output [ADDR_WIDTH-1:0] cam_addr_out;
output cam_hit_out;
output [ADDR_WIDTH-1:0] cam_addr_out;
//------------Internal Variables--------
reg [ADDR_WIDTH-1:0] cam_addr_out;
reg cam_hit_out;
@ -46,7 +46,7 @@ always @(cam_data_in) begin
end
end
// Register the outputs
// Register the outputs
always @(posedge clk) begin
if (cam_enable) begin
cam_hit_out <= cam_hit_combo;
@ -57,4 +57,4 @@ always @(posedge clk) begin
end
end
endmodule
endmodule

12
tests/asicworld/code_hdl_models_clk_div.v
View file

@ -6,7 +6,7 @@
//-----------------------------------------------------
module clk_div (clk_in, enable,reset, clk_out);
// --------------Port Declaration-----------------------
// --------------Port Declaration-----------------------
input clk_in ;
input reset ;
input enable ;
@ -16,12 +16,12 @@ module clk_div (clk_in, enable,reset, clk_out);
wire enable ;
//--------------Internal Registers----------------------
reg clk_out ;
//--------------Code Starts Here-----------------------
always @ (posedge clk_in)
if (reset) begin
//--------------Code Starts Here-----------------------
always @ (posedge clk_in)
if (reset) begin
clk_out <= 1'b0;
end else if (enable) begin
clk_out <= !clk_out ;
clk_out <= !clk_out ;
end
endmodule
endmodule

4
tests/asicworld/code_hdl_models_clk_div_45.v
View file

@ -28,7 +28,7 @@ reg toggle2 ;
//--------------Code Starts Here-----------------------
always @ (posedge clk_in)
if (enable == 1'b0) begin
if (enable == 1'b0) begin
counter1 <= 4'b0;
toggle1 <= 0;
end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
@ -37,7 +37,7 @@ end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
end else begin
counter1 <= counter1 + 1;
end
always @ (negedge clk_in)
if (enable == 1'b0) begin
counter2 <= 4'b0;

10
tests/asicworld/code_hdl_models_decoder_using_assign.v
View file

@ -6,14 +6,14 @@
//-----------------------------------------------------
module decoder_using_assign (
binary_in , // 4 bit binary input
decoder_out , // 16-bit out
decoder_out , // 16-bit out
enable // Enable for the decoder
);
input [3:0] binary_in ;
input enable ;
output [15:0] decoder_out ;
wire [15:0] decoder_out ;
input enable ;
output [15:0] decoder_out ;
wire [15:0] decoder_out ;
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;

4
tests/asicworld/code_hdl_models_dff_async_reset.v
View file

@ -7,11 +7,11 @@
module dff_async_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
input data, clk, reset ;
//-----------Output Ports---------------
output q;

2
tests/asicworld/code_hdl_models_dff_sync_reset.v
View file

@ -11,7 +11,7 @@ reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
input data, clk, reset ;
//-----------Output Ports---------------
output q;

34
tests/asicworld/code_hdl_models_encoder_using_case.v
View file

@ -10,31 +10,31 @@ encoder_in , // 16-bit Input
enable // Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
input enable ;
input [15:0] encoder_in ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
16'h0010 : binary_out = 4;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0100 : binary_out = 8;
16'h0200 : binary_out = 9;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
endcase
end
end

66
tests/asicworld/code_hdl_models_encoder_using_if.v
View file

@ -8,51 +8,51 @@ module encoder_using_if(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
);
//-----------Output Ports---------------
output [3:0] binary_out ;
//-----------Input Ports---------------
input enable ;
input [15:0] encoder_in ;
input enable ;
input [15:0] encoder_in ;
//------------Internal Variables--------
reg [3:0] binary_out ;
reg [3:0] binary_out ;
//-------------Code Start-----------------
always @ (enable or encoder_in)
begin
binary_out = 0;
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
end if (encoder_in == 16'h0008) begin
binary_out = 3;
end if (encoder_in == 16'h0010) begin
binary_out = 4;
end if (encoder_in == 16'h0020) begin
binary_out = 5;
end if (encoder_in == 16'h0040) begin
binary_out = 6;
end if (encoder_in == 16'h0080) begin
binary_out = 7;
end if (encoder_in == 16'h0100) begin
binary_out = 8;
end if (encoder_in == 16'h0200) begin
binary_out = 9;
end if (encoder_in == 16'h0400) begin
binary_out = 10;
end if (encoder_in == 16'h0800) begin
binary_out = 11;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
end if (encoder_in == 16'h0008) begin
binary_out = 3;
end if (encoder_in == 16'h0010) begin
binary_out = 4;
end if (encoder_in == 16'h0020) begin
binary_out = 5;
end if (encoder_in == 16'h0040) begin
binary_out = 6;
end if (encoder_in == 16'h0080) begin
binary_out = 7;
end if (encoder_in == 16'h0100) begin
binary_out = 8;
end if (encoder_in == 16'h0200) begin
binary_out = 9;
end if (encoder_in == 16'h0400) begin
binary_out = 10;
end if (encoder_in == 16'h0800) begin
binary_out = 11;
end if (encoder_in == 16'h1000) begin
binary_out = 12;
end if (encoder_in == 16'h2000) begin
binary_out = 12;
end if (encoder_in == 16'h2000) begin
binary_out = 13;
end if (encoder_in == 16'h4000) begin
binary_out = 14;
end if (encoder_in == 16'h8000) begin
binary_out = 15;
end if (encoder_in == 16'h4000) begin
binary_out = 14;
end if (encoder_in == 16'h8000) begin
binary_out = 15;
end
end
end
endmodule

26
tests/asicworld/code_hdl_models_gray_counter.v
View file

@ -10,24 +10,24 @@ module gray_counter (
clk , // clock
rst // active hight reset
);
//------------Input Ports--------------
input clk, rst, enable;
input clk, rst, enable;
//----------Output Ports----------------
output [ 7:0] out;
//------------Internal Variables--------
wire [7:0] out;
reg [7:0] count;
//-------------Code Starts Here---------
always @ (posedge clk)
if (rst)
count <= 0;
else if (enable)
count <= count + 1;
assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
count[5]),(count[5] ^ count[4]), (count[4] ^
count[3]),(count[3] ^ count[2]), (count[2] ^
always @ (posedge clk)
if (rst)
count <= 0;
else if (enable)
count <= count + 1;
assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
count[5]),(count[5] ^ count[4]), (count[4] ^
count[3]),(count[3] ^ count[2]), (count[2] ^
count[1]),(count[1] ^ count[0]) };
endmodule
endmodule

2
tests/asicworld/code_hdl_models_lfsr.v
View file

@ -30,6 +30,6 @@ end else if (enable) begin
out[4],out[3],
out[2],out[1],
out[0], linear_feedback};
end
end
endmodule // End Of Module counter

8
tests/asicworld/code_hdl_models_lfsr_updown.v
View file

@ -1,4 +1,4 @@
`define WIDTH 8
`define WIDTH 8
module lfsr_updown (
clk , // Clock input
reset , // Reset input
@ -10,7 +10,7 @@ overflow // Overflow output
input clk;
input reset;
input enable;
input enable;
input up_down;
output [`WIDTH-1 : 0] count;
@ -18,11 +18,11 @@ overflow // Overflow output
reg [`WIDTH-1 : 0] count;
assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :
assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :
(count == {1'b1, {`WIDTH-1{1'b0}}}) ;
always @(posedge clk)
if (reset)
if (reset)
count <= {`WIDTH{1'b0}};
else if (enable) begin
if (up_down) begin

4
tests/asicworld/code_hdl_models_mux_using_case.v
View file

@ -19,10 +19,10 @@ reg mux_out;
//-------------Code Starts Here---------
always @ (sel or din_0 or din_1)
begin : MUX
case(sel )
case(sel )
1'b0 : mux_out = din_0;
1'b1 : mux_out = din_1;
endcase
endcase
end
endmodule //End Of Module mux

4
tests/asicworld/code_hdl_models_one_hot_cnt.v
View file

@ -17,7 +17,7 @@ output [7:0] out;
input enable, clk, reset;
//------------Internal Variables--------
reg [7:0] out;
reg [7:0] out;
//-------------Code Starts Here-------
always @ (posedge clk)
@ -28,4 +28,4 @@ end else if (enable) begin
out[2],out[1],out[0],out[7]};
end
endmodule
endmodule

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