Move rename logic to abc_ops_reintegrate

tests/aiger/neg.ys

@@ -1,36 +0,0 @@
-read_verilog <<EOT
-module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
-assign c = a & b;
-endmodule
-EOT
-select -assert-count 1 i:a
-select -assert-count 1 i:b
-select -assert-count 1 o:c
-select -assert-count 3 x:* s:64 %i
-design -save read
-
-!rm -rf neg.out
-!mkdir neg.out
-simplemap
-write_aiger -map neg.out/neg.map neg.out/neg.aig
-
-design -reset
-read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
-select -assert-count 1 i:a
-select -assert-count 1 i:b
-select -assert-count 1 o:c
-select -assert-count 3 x:* s:64 %i
-
-
-design -load read
-!rm -rf neg.out
-!mkdir neg.out
-simplemap
-write_xaiger -map neg.out/neg.map neg.out/neg.aig
-
-design -reset
-read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
-select -assert-count 1 i:a
-select -assert-count 1 i:b
-select -assert-count 1 o:c
-select -assert-count 3 x:* s:64 %i

tests/arch/analogdevices/logic.ys

@@ -5,7 +5,7 @@ equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:LUT1
-select -assert-count 6 t:LUT2
+select -assert-count 4 t:LUT1
+select -assert-count 3 t:LUT2
 select -assert-count 2 t:LUT4
 select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D

tests/arch/gowin/logic.ys

@@ -5,8 +5,8 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:LUT1
-select -assert-count 6 t:LUT2
+select -assert-count 4 t:LUT1
+select -assert-count 3 t:LUT2
 select -assert-count 2 t:LUT4
 select -assert-count 8 t:IBUF
 select -assert-count 10 t:OBUF

tests/arch/intel_alm/logic.ys

@@ -5,8 +5,8 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:MISTRAL_NOT
-select -assert-count 6 t:MISTRAL_ALUT2
+select -assert-count 4 t:MISTRAL_NOT
+select -assert-count 3 t:MISTRAL_ALUT2
 select -assert-count 2 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
 

tests/arch/quicklogic/pp3/logic.ys

@@ -5,8 +5,8 @@ equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cel
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:LUT1
-select -assert-count 6 t:LUT2
+select -assert-count 4 t:LUT1
+select -assert-count 3 t:LUT2
 select -assert-count 2 t:LUT3
 select -assert-count 8 t:inpad
 select -assert-count 10 t:outpad

tests/various/abc9.v

@@ -1,15 +1,3 @@
-module abc9_test027(output reg o);
-initial o = 1'b0;
-always @*
-    o <= ~o;
-endmodule
-
-module abc9_test028(input i, output o);
-wire w;
-unknown u(~i, w);
-unknown2 u2(w, o);
-endmodule
-
 module abc9_test032(input clk, d, r, output reg q);
 initial q = 1'b0;
 always @(negedge clk or negedge r)

tests/various/abc9.ys

@@ -1,31 +1,4 @@
 read_verilog abc9.v
-design -save read
-hierarchy -top abc9_test027
-proc
-design -save gold
-
-abc9 -lut 4
-check
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-
-design -load read
-hierarchy -top abc9_test028
-proc
-
-abc9 -lut 4
-select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
-select -assert-count 1 t:unknown
-select -assert-none t:$lut t:unknown %% t: %D
-
-
-design -load read
 hierarchy -top abc9_test032
 proc
 clk2fflogic