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Fix covers_nothing.

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This commit is contained in:
nella 2026-07-06 13:26:00 +02:00
parent 6a45e7b290
commit 2b4ec9d57a
3 changed files with 72 additions and 10 deletions
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10
tests/unit/kernel/bitpatternTest.cc
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@ -11,6 +11,8 @@ TEST(BitpatternTest, has)
SigSpec _01a = {RTLIL::S0, RTLIL::S1, RTLIL::Sa};
SigSpec _011 = {RTLIL::S0, RTLIL::S1, RTLIL::S1};
SigSpec _111 = {RTLIL::S1, RTLIL::S1, RTLIL::S1};
SigSpec _01x = {RTLIL::S0, RTLIL::S1, RTLIL::Sx};
SigSpec _01z = {RTLIL::S0, RTLIL::S1, RTLIL::Sz};
EXPECT_TRUE(BitPatternPool(_aaa).has_any(_01a));
EXPECT_TRUE(BitPatternPool(_01a).has_any(_01a));
@ -19,6 +21,10 @@ TEST(BitpatternTest, has)
// overlap is symmetric
EXPECT_TRUE(BitPatternPool(_01a).has_any(_011));
EXPECT_FALSE(BitPatternPool(_111).has_any(_01a));
// overlaps nothing
EXPECT_FALSE(BitPatternPool(_011).has_any(_01x));
EXPECT_FALSE(BitPatternPool(_011).has_any(_01z));
EXPECT_FALSE(BitPatternPool(_aaa).has_any(_01x));
EXPECT_TRUE(BitPatternPool(_aaa).has_all(_01a));
EXPECT_TRUE(BitPatternPool(_01a).has_all(_01a));
@ -27,6 +33,10 @@ TEST(BitpatternTest, has)
// 01a is not covered by 011
EXPECT_FALSE(BitPatternPool(_011).has_all(_01a));
EXPECT_FALSE(BitPatternPool(_111).has_all(_01a));
// trivially covered by any pool
EXPECT_TRUE(BitPatternPool(_011).has_all(_01x));
EXPECT_TRUE(BitPatternPool(_011).has_all(_01z));
EXPECT_TRUE(BitPatternPool(_111).has_all(_01x));
}
YOSYS_NAMESPACE_END

48
tests/verilog/temp/issue4402_syn.v Normal file
View file

@ -0,0 +1,48 @@
/* Generated by Yosys 0.66+154 (git sha1 23aadd92a-dirty, Release, Clang /nix/store/mw4gasdvwgscgpxpzihjgchfhs3hhqhn-clang-wrapper-21.1.8/bin/clang++ 21.1.8) [git@github.com:YosysHQ/yosys at nella/x-wildcard] */
(* top = 1 *)
(* src = "<<EOT:1.1-12.10" *)
module top(y, clk, wire0);
(* src = "<<EOT:2.15-2.16" *)
output y;
wire y;
(* src = "<<EOT:3.14-3.17" *)
input clk;
wire clk;
(* src = "<<EOT:4.21-4.26" *)
input signed wire0;
wire signed wire0;
(* src = "<<EOT:9.3-11.6" *)
wire _0_;
(* src = "<<EOT:6.7-6.15" *)
wire _1_;
(* src = "<<EOT:7.7-7.15" *)
wire _2_;
(* src = "<<EOT:10.21-10.31" *)
wire _3_;
(* src = "<<EOT:10.45-10.50" *)
wire _4_;
(* src = "<<EOT:10.55-10.70" *)
wire _5_;
(* src = "<<EOT:10.13-10.71" *)
wire _6_;
(* src = "<<EOT:5.7-5.11" *)
reg reg1;
(* src = "<<EOT:6.7-6.11" *)
wire var2;
(* src = "<<EOT:7.7-7.11" *)
wire var3;
assign _3_ = $signed(wire0) <= (* src = "<<EOT:10.21-10.31" *) $signed(32'd0);
(* src = "<<EOT:9.3-11.6" *)
always @(posedge clk)
reg1 <= _6_;
assign _6_ = _3_ ? (* src = "<<EOT:10.13-10.71" *) 1'h0 : 1'h1;
assign y = reg1;
assign _2_ = 1'h0;
assign _1_ = 1'h0;
assign _0_ = _6_;
assign var3 = 1'h0;
assign var2 = 1'h0;
assign _4_ = var3;
assign _5_ = 1'h1;
endmodule