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Merge pull request #5952 from YosysHQ/nella/vector-index

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Optimize upto vector indexing (Fix #892).
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nella 2026-06-22 09:05:26 +00:00 • committed by GitHub
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tests/arch/xilinx/dynamic_upto_select.ys Normal file
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# https://github.com/YosysHQ/yosys/issues/892
read_verilog <<EOT
module top (input clk, sel, di, output do);
reg [0:1] data [0:0];
always @(posedge clk)
data[0] <= {di, data[0][0]};
assign do = data[0][sel];
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
design -load postopt
select -assert-count 1 t:BUFG
select -assert-count 2 t:FDRE
select -assert-count 1 t:LUT3
select -assert-none t:BUFG t:FDRE t:LUT3 %% t:* %D

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tests/opt/opt_expr_sub_not.ys Normal file
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# Rewrite (2^k-1)-x into ~x when x is known to be smaller than 2^k
read_verilog -icells <<EOT
module test(input [3:0] b, output [3:0] y);
$sub #(
.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
.A_SIGNED(0), .B_SIGNED(0),
) sub (
.A(4'hf), .B(b), .Y(y),
);
endmodule
EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$not
select -assert-none t:$sub
select -assert-none t:$not t:* %D
design -reset
read_verilog -icells <<EOT
module test(input [1:0] b, output [3:0] y);
$sub #(
.A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(4),
.A_SIGNED(0), .B_SIGNED(0),
) sub (
.A(4'd3), .B(b), .Y(y),
);
endmodule
EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$not
select -assert-none t:$sub
design -reset
read_verilog -icells <<EOT
module test(input [3:0] b, output [3:0] y);
$sub #(
.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
.A_SIGNED(0), .B_SIGNED(0),
) sub (
.A(4'b1011), .B(b), .Y(y),
);
endmodule
EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-none t:$not
design -reset
read_verilog -icells <<EOT
module test(input [3:0] b, output [3:0] y);
$sub #(
.A_WIDTH(2), .B_WIDTH(4), .Y_WIDTH(4),
.A_SIGNED(0), .B_SIGNED(0),
) sub (
.A(2'b11), .B(b), .Y(y),
);
endmodule
EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-none t:$not
design -reset
read_verilog <<EOT
module test(input [1:0] sel, input [0:3] data, output out);
assign out = data[sel];
endmodule
EOT
equiv_opt -assert opt -full
design -load postopt
select -assert-none t:$sub t:$add t:$alu
design -reset
read_verilog <<EOT
module test(input sel, input [0:1] data, output out);
assign out = data[sel];
endmodule
EOT
equiv_opt -assert opt -full
design -load postopt
select -assert-none t:$sub t:$add t:$alu