3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-14 11:15:40 +00:00

Merge pull request #6023 from b-michi/michaelbaier/sc-649/segmentation-fault-during-proc-init-with

Michaelbaier/sc 649/segmentation fault during proc init with
This commit is contained in:
nella 2026-07-10 13:07:58 +00:00 committed by GitHub
commit ede98b81ac
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
14 changed files with 115 additions and 16 deletions

6
tests/rtlil/bug1206.ys Normal file
View file

@ -0,0 +1,6 @@
logger -expect error "Wire width .* out of range" 1
read_rtlil <<EOT
module \foo
wire width 1073741824 \bar
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Memory width .* out of range" 1
read_rtlil <<EOT
module \foo
memory width 1073741824 \mem
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Memory offset .* out of range" 1
read_rtlil <<EOT
module \foo
memory width 8 offset -4294967396 \mem
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Memory offset .* out of range" 1
read_rtlil <<EOT
module \foo
memory width 8 offset 4294967396 \mem
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Memory width .* out of range" 1
read_rtlil <<EOT
module \foo
memory width 4294967396 \mem
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Memory size .* out of range" 1
read_rtlil <<EOT
module \foo
memory width 8 size 4294967396 \mem
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Wire width .* out of range" 1
read_rtlil <<EOT
module \foo
wire width 4294967396 \bar
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Wire offset .* out of range" 1
read_rtlil <<EOT
module \foo
wire width 8 offset -4294967396 \bar
end
EOT

View file

@ -0,0 +1,6 @@
logger -expect error "Wire offset .* out of range" 1
read_rtlil <<EOT
module \foo
wire width 8 offset 4294967396 \bar
end
EOT

View file

@ -284,6 +284,28 @@ namespace RTLIL {
EXPECT_EQ(c, Const(0xe, 4));
}
TEST_F(KernelRtlilTest, ConstResizeWidthLimit) {
Const c;
EXPECT_DEATH(c.resize(RTLIL::WIDTH_LIMIT, Sx), "");
EXPECT_NO_FATAL_FAILURE(c.resize(RTLIL::WIDTH_LIMIT - 1, Sx));
}
TEST_F(KernelRtlilTest, ConstFromLongLongWidthLimit) {
EXPECT_DEATH(Const(0, RTLIL::WIDTH_LIMIT), "");
EXPECT_NO_FATAL_FAILURE(Const(0, RTLIL::WIDTH_LIMIT - 1));
}
TEST_F(KernelRtlilTest, ConstFromStateWidthLimit) {
EXPECT_DEATH(Const(Sx, RTLIL::WIDTH_LIMIT), "");
EXPECT_NO_FATAL_FAILURE(Const(Sx, RTLIL::WIDTH_LIMIT - 1));
}
TEST_F(KernelRtlilTest, ModuleAddWireWidthLimit) {
std::unique_ptr<Module> mod = std::make_unique<Module>();
EXPECT_DEATH(mod->addWire(ID(test), RTLIL::WIDTH_LIMIT), "");
EXPECT_NO_FATAL_FAILURE(mod->addWire(ID(test), RTLIL::WIDTH_LIMIT - 1));
}
TEST_F(KernelRtlilTest, ConstEqualStr) {
EXPECT_EQ(Const("abc"), Const("abc"));
EXPECT_NE(Const("abc"), Const("def"));