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8869ce61dc · Merge pull request #5955 from YosysHQ/krys/mod_name · Updated 2026-06-14 21:29:12 +00:00

Branches

25f7dd6650 · Latest fixes · Updated 2026-06-12 14:40:55 +00:00

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ea70de2165 · Use read_techlib where applicable in tests · Updated 2026-06-12 13:27:48 +00:00

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02f4d74ebe · handle in btor backend · Updated 2026-06-11 15:36:44 +00:00

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83a8245734 · Add muxcover regression test. · Updated 2026-06-10 12:46:04 +00:00

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601cd7ba5f · Add tests. · Updated 2026-06-10 09:30:03 +00:00

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9cd7445252 · wip · Updated 2026-06-10 09:01:25 +00:00

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bbb6841b91 · symfpu: whitespace · Updated 2026-06-05 22:04:43 +00:00

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5328762fe5 · Add regtype checks to tests. · Updated 2026-06-03 10:51:57 +00:00

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2f82b3aed5 · docs: Remove build dir from tool help · Updated 2026-06-03 00:00:19 +00:00

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68df0be7d2 · Remove eqbits flag. · Updated 2026-05-25 12:16:55 +00:00

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5a6568edbe · rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design · Updated 2026-05-22 23:09:26 +00:00

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849526491a · fixup! tests: signorm fix · Updated 2026-05-22 19:23:38 +00:00

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886d0a7043 · Merge branch 'main' into gus/sim-with-vcd-tuneup · Updated 2026-05-19 10:17:29 +00:00

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38c2806636 · Make sure to apply correct signedness to loop vars. · Updated 2026-05-13 14:52:07 +00:00

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7d3e56523b · Preserve param signedness across overrides. · Updated 2026-05-13 14:25:15 +00:00

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334dd7b80c · muxpack: reject slicing of predecessor Y ports in mux chain · Updated 2026-05-13 08:27:05 +00:00

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d55f4daae2 · Cleanup. · Updated 2026-05-12 15:06:57 +00:00

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d9faee0153 · Accumulate connect cells. · Updated 2026-05-12 12:47:49 +00:00

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b04aadfa44 · Add LogSink & LogMessage classes for a more robust sink solution. · Updated 2026-05-06 16:23:24 +00:00

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77b63be4d2 · Remove unstable san test for mac. · Updated 2026-05-06 11:44:10 +00:00

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