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6900818105 · Bump version · Updated 2025-05-10 00:22:55 +00:00

Branches

586fa033a6 · design: ensure all_modules outlives pass when building WITH_PYTHON · Updated 2025-05-10 15:19:51 +00:00

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10ea2fa67e · ast.h: Move attribute check into set · Updated 2025-05-10 05:24:13 +00:00

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fe0abb7026 · simplify.cc: Fix mem leak · Updated 2025-05-10 05:10:47 +00:00

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af75dce660 · Fix Crashes with GCC 15 #5088 · Updated 2025-05-09 21:59:13 +00:00

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1e2d6508d0 · Makefile: Conditional assignment of python exe · Updated 2025-05-09 21:09:30 +00:00

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2e9a194ce9 · gzip: reject uncompressing directories · Updated 2025-05-09 20:33:30 +00:00

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cbf069849e · aiger: add regression test for sliced output segfault · Updated 2025-05-09 14:01:47 +00:00

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2ca2ecaa1c · libcache: fix help · Updated 2025-05-09 10:40:45 +00:00

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068dd77a14 · check: fix up tests · Updated 2025-05-08 13:30:49 +00:00

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547382504b · Update verilog_frontend.cc · Updated 2025-05-07 22:37:04 +00:00

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68c11321c0 · remove invalid tests · Updated 2025-05-07 15:52:31 +00:00

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90a2c92370 · driver: allow --no-version still write things like Generated by Yosys · Updated 2025-05-07 09:34:23 +00:00

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a4d23c0847 · fixup! rtlil: enable single-bit vector wires · Updated 2025-05-06 14:57:34 +00:00

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7c89355b70 · cutpoint: Re-add whole module optimization · Updated 2025-05-05 21:57:34 +00:00

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b7dcdec745 · sdc: add initial stubbed demo · Updated 2025-05-02 15:48:33 +00:00

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414a1bf278 · autoname: Check for potential overflow · Updated 2025-04-30 23:57:49 +00:00

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11c846de5c · aiger, xaiger, aiger2: add -no_version · Updated 2025-04-30 17:51:35 +00:00

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adb1986dc1 · gzip: refactor file open failure errors · Updated 2025-04-29 08:37:35 +00:00

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ff2a8af545 · quicklogic: workaround for #5069 · Updated 2025-04-28 14:01:12 +00:00

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f0545d5bc1 · simplify: fix another struct wiretype attr memory leak · Updated 2025-04-28 11:18:00 +00:00

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