3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-05 05:41:24 +00:00

Default branch

50b63c6481 · Bump version · Updated 2025-06-05 00:24:30 +00:00

Branches

c37b7b3bf4 · simplify: fix single_bit_vector memory leak · Updated 2025-06-04 08:32:03 +00:00

8
0
Included

784de0f6e3 · Make attrmap able to alter memory attributes as well · Updated 2025-06-04 06:01:21 +00:00

24
1

785cabcb0f · abc9_ops: Skip opt_expr in proc · Updated 2025-05-31 00:16:37 +00:00

18
2

6e3922e1c7 · functional.cc: Explicit unsorted-pool-as-LIFO · Updated 2025-05-30 21:57:43 +00:00

59
3

e421a03d5a · CODEOWNERS: add myself for the ABC doc · Updated 2025-05-30 21:05:54 +00:00

21
0
Included

6cd5921c2e · hashlib: break dict by reversing the iterator order · Updated 2025-05-30 14:43:55 +00:00

22
1

05f2ce2f4b · sdc: wip regex · Updated 2025-05-28 10:42:05 +00:00

112
9

33376da034 · ConstParser instead of const2ast using global state · Updated 2025-05-26 15:16:24 +00:00

43
9

a9d4579765 · advanced_bugpoint.rst: Paragraphing · Updated 2025-05-22 22:52:54 +00:00

50
22

6a7ecf12f1 · fixup! ast, read_verilog: ownership in AST, use C++ styles for parser and lexer · Updated 2025-05-21 11:02:03 +00:00

83
2

20b0ab26b1 · tests/bugpoint: More tests · Updated 2025-05-16 04:55:54 +00:00

74
11

45452c18b2 · write_verilog: write module ports in order · Updated 2025-05-14 12:34:50 +00:00

83
1

f73c6a9c9a · write_verilog: don't dump single_bit_vector attribute · Updated 2025-05-12 11:36:25 +00:00

98
0
Included

586fa033a6 · design: ensure all_modules outlives pass when building WITH_PYTHON · Updated 2025-05-10 15:19:51 +00:00

83
1

2e9a194ce9 · gzip: reject uncompressing directories · Updated 2025-05-09 20:33:30 +00:00

85
0
Included

cbf069849e · aiger: add regression test for sliced output segfault · Updated 2025-05-09 14:01:47 +00:00

99
0
Included

2ca2ecaa1c · libcache: fix help · Updated 2025-05-09 10:40:45 +00:00

98
0
Included

068dd77a14 · check: fix up tests · Updated 2025-05-08 13:30:49 +00:00

187
6

547382504b · Update verilog_frontend.cc · Updated 2025-05-07 22:37:04 +00:00

93
1

68c11321c0 · remove invalid tests · Updated 2025-05-07 15:52:31 +00:00

187
3