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gowin: infer DSP multiply-accumulate for the GW5A family
Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.
The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).
alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
This commit is contained in:
Johan Olby
parent
0e82bbefe5
commit
4d215665a1
5 changed files with 198 additions and 0 deletions
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@ -52,4 +52,5 @@ yosys_pass(synth_gowin
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lutrams_map.v
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lutrams.txt
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dsp_map.v
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macc_map_gw5a.v
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)
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59
techlibs/gowin/macc_map_gw5a.v
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59
techlibs/gowin/macc_map_gw5a.v
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@ -0,0 +1,59 @@
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module \$macc_v2 (A, B, C, Y);
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parameter NPRODUCTS = 0;
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parameter PRODUCT_NEGATED = 1'b0;
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parameter NADDENDS = 0;
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parameter ADDEND_NEGATED = 1'b0;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter C_SIGNED = 0;
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parameter A_WIDTHS = 1;
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parameter B_WIDTHS = 1;
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parameter C_WIDTHS = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTHS-1:0] A;
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input [B_WIDTHS-1:0] B;
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input [C_WIDTHS-1:0] C;
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output [Y_WIDTH-1:0] Y;
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wire _TECHMAP_FAIL_ = !(NPRODUCTS == 1 && NADDENDS == 1 &&
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PRODUCT_NEGATED == 1'b0 && ADDEND_NEGATED == 1'b0 &&
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A_SIGNED && B_SIGNED && C_SIGNED &&
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A_WIDTHS <= 27 && B_WIDTHS <= 18 && C_WIDTHS <= 48);
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wire [47:0] dout_w;
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MULTALU27X18 #(
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.MULT12X12_EN("FALSE"),
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.MULT_RESET_MODE("SYNC"),
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.AREG_CLK("BYPASS"),
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.BREG_CLK("BYPASS"),
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.PREG_CLK("BYPASS"),
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.OREG_CLK("BYPASS"),
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.DYN_C_SEL("TRUE")
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) __TECHMAP_REPLACE__ (
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.DOUT(dout_w),
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.CASO(),
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.SOA(),
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.A(A),
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.SIA(27'd0),
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.B(B),
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.C(C),
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.D(26'd0),
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.CASI(48'd0),
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.ACCSEL(1'b0),
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.PSEL(1'b0),
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.ASEL(1'b0),
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.PADDSUB(1'b0),
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.CSEL(1'b1),
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.CASISEL(1'b0),
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.ADDSUB(2'b00),
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.CLK(2'b00),
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.CE(2'b00),
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.RESET(2'b00)
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);
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assign Y = dout_w;
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endmodule
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@ -277,6 +277,13 @@ struct SynthGowinPass : public ScriptPass
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run("opt -nodffe -nosdff");
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run("fsm");
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run("opt");
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// GW5A MAC: run alumacc + macc techmap BEFORE wreduce. wreduce
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// narrows $mul Y but not the connected $add A, leaving a width
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// mismatch that prevents alumacc from merging $mul into $add.
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if (!nodsp && family == "gw5a") {
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run("alumacc");
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run("techmap -map +/gowin/macc_map_gw5a.v");
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}
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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44
tests/arch/gowin/macc_gw5a.v
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44
tests/arch/gowin/macc_gw5a.v
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@ -0,0 +1,44 @@
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module top
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#(parameter X_WIDTH=8, Y_WIDTH=8, C_WIDTH=16, A_WIDTH=16)
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(
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input signed [X_WIDTH-1:0] x,
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input signed [Y_WIDTH-1:0] y,
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input signed [C_WIDTH-1:0] c,
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output signed [A_WIDTH-1:0] A
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);
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assign A = x * y + c;
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endmodule
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module sub_top
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#(parameter X_WIDTH=8, Y_WIDTH=8, C_WIDTH=16, A_WIDTH=16)
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(
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input signed [X_WIDTH-1:0] x,
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input signed [Y_WIDTH-1:0] y,
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input signed [C_WIDTH-1:0] c,
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output signed [A_WIDTH-1:0] A
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);
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assign A = x * y - c;
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endmodule
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module twoproduct_top
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#(parameter X_WIDTH=8, Y_WIDTH=8, C_WIDTH=16, A_WIDTH=16)
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(
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input signed [X_WIDTH-1:0] x,
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input signed [Y_WIDTH-1:0] y,
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input signed [C_WIDTH-1:0] c,
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output signed [A_WIDTH-1:0] A
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);
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wire signed [X_WIDTH+Y_WIDTH-1:0] p = x * y;
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assign A = p + p;
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endmodule
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module unsigned_top
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#(parameter X_WIDTH=8, Y_WIDTH=8, C_WIDTH=16, A_WIDTH=16)
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(
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input [X_WIDTH-1:0] x,
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input [Y_WIDTH-1:0] y,
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input [C_WIDTH-1:0] c,
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output [A_WIDTH-1:0] A
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);
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assign A = x * y + c;
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endmodule
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87
tests/arch/gowin/macc_gw5a.ys
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87
tests/arch/gowin/macc_gw5a.ys
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@ -0,0 +1,87 @@
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# GW5A DSP MAC ($macc_v2) inference tests.
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# 27x18 + 48-bit addend -> 1 MULTALU27X18 (MAC)
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set C_WIDTH 48 -set A_WIDTH 48
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hierarchy -top top
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proc
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synth_gowin -family gw5a
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cd top
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select -assert-count 1 t:MULTALU27X18
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# Make sure that DSPs are not inferred with -nodsp option
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design -reset
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set C_WIDTH 48 -set A_WIDTH 48
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hierarchy -top top
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proc
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synth_gowin -family gw5a -nodsp
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cd top
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select -assert-none t:MULTALU27X18
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# A operand exceeds 27 -> _TECHMAP_FAIL_ (A_WIDTHS > 27)
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design -reset
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 28 -set Y_WIDTH 18 -set C_WIDTH 48 -set A_WIDTH 48
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hierarchy -top top
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proc
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synth_gowin -family gw5a
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cd top
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select -assert-none t:MULTALU27X18
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# B operand exceeds 18 -> _TECHMAP_FAIL_ (B_WIDTHS > 18)
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design -reset
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 27 -set Y_WIDTH 19 -set C_WIDTH 48 -set A_WIDTH 48
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hierarchy -top top
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proc
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synth_gowin -family gw5a
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cd top
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select -assert-none t:MULTALU27X18
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# C addend exceeds 48 -> _TECHMAP_FAIL_ (C_WIDTHS > 48)
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design -reset
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set C_WIDTH 49 -set A_WIDTH 49
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hierarchy -top top
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proc
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synth_gowin -family gw5a
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cd top
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select -assert-none t:MULTALU27X18
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# Addend negated (a*b - c) -> _TECHMAP_FAIL_ (ADDEND_NEGATED)
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design -reset
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set C_WIDTH 48 -set A_WIDTH 48
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hierarchy -top sub_top
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proc
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synth_gowin -family gw5a
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cd sub_top
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select -assert-none t:MULTALU27X18
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# Two products (a*b + a*b) -> _TECHMAP_FAIL_ (NPRODUCTS != 1)
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design -reset
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set C_WIDTH 48 -set A_WIDTH 48
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hierarchy -top twoproduct_top
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proc
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synth_gowin -family gw5a
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cd twoproduct_top
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select -assert-none t:MULTALU27X18
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# Unsigned operands -> _TECHMAP_FAIL_ (!A_SIGNED)
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design -reset
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read_verilog macc_gw5a.v
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chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set C_WIDTH 48 -set A_WIDTH 48
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hierarchy -top unsigned_top
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proc
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synth_gowin -family gw5a
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cd unsigned_top
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select -assert-none t:MULTALU27X18
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