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Fix (async latch).

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nella 2026-06-24 13:01:52 +02:00
parent a800a5b5cb
commit 6675c45e29
1 changed files with 2 additions and 2 deletions
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4
tests/various/check_nolatches.ys
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@ -1,7 +1,7 @@
design -reset
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
module top(input g, d, output reg q);
always @* if (g) q = d;
endmodule
EOT
hierarchy -top top