Error out on latches.

tests/arch/ecp5/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
+synth_ecp5 -latches auto
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT4
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
+synth_ecp5 -latches auto
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT4
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
+synth_ecp5 -latches auto
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:LUT4
 select -assert-count 1 t:PFUMX

tests/arch/ecp5/latches_abc9.ys

@@ -8,6 +8,6 @@ assign q = ~l;
 endmodule
 EOT
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5 -abc9
+synth_ecp5 -abc9 -latches auto
 select -assert-count 2 t:LUT4
 select -assert-none t:LUT4 %% t:* %D

tests/arch/efinix/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_efinix -latches auto
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_LUT4
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_efinix -latches auto
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_LUT4
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_efinix
+synth_efinix -latches auto
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:EFX_LUT4
 

tests/arch/ice40/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ice40
+synth_ice40 -latches auto
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_LUT4
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ice40
+synth_ice40 -latches auto
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_LUT4
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ice40
+synth_ice40 -latches auto
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:SB_LUT4
 

tests/arch/nanoxplore/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore -noiopad
+synth_nanoxplore -noiopad -latches auto
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
 
@@ -15,7 +15,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore -noiopad
+synth_nanoxplore -noiopad -latches auto
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:NX_LUT
 
@@ -26,7 +26,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_nanoxplore -noiopad
+synth_nanoxplore -noiopad -latches auto
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 2 t:NX_LUT
 

tests/arch/quicklogic/pp3/latches.ys

@@ -4,7 +4,7 @@ design -save read
 hierarchy -top latchp
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic
+synth_quicklogic -latches auto
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
 select -assert-count 3 t:inpad
@@ -17,7 +17,7 @@ design -load read
 hierarchy -top latchn
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic
+synth_quicklogic -latches auto
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT3
 select -assert-count 3 t:inpad
@@ -30,7 +30,7 @@ design -load read
 hierarchy -top latchsr
 proc
 # Can't run any sort of equivalence check because latches are blown to LUTs
-synth_quicklogic
+synth_quicklogic -latches auto
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LUT2
 select -assert-count 1 t:LUT4

tests/various/synth_latch_warning.ys

@@ -3,6 +3,17 @@ module top(input d, en, output reg q);
 always @* if (en) q = d;
 endmodule
 EOT
-logger -expect warning "is a latch of type" 1
-synth_ice40
+design -save read
+
+logger -expect warning "Latch inferred for signal" 1
+synth_ice40 -latches warn
 logger -check-expected
+select -assert-count 1 t:SB_LUT4
+
+design -load read
+synth_ice40 -latches auto
+select -assert-count 1 t:SB_LUT4
+
+design -load read
+logger -expect error "selection is not empty: t:._DLATCH_" 1
+synth_ice40