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Emit latch warning.

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nella 2026-06-17 11:27:43 +02:00
parent a46bc77eeb
commit c814ef35e3
7 changed files with 16 additions and 1 deletions
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8
tests/various/synth_latch_warning.ys Normal file
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@ -0,0 +1,8 @@
read_verilog <<EOT
module top(input d, en, output reg q);
always @* if (en) q = d;
endmodule
EOT
logger -expect warning "is a latch of type" 1
synth_ice40
logger -check-expected