End of file fix

tests/arch/analogdevices/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 2 t:RBRAM2
-

tests/arch/analogdevices/dffs.ys

@@ -38,4 +38,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:FFRE
 select -assert-none t:FFRE %% t:* %D
-

tests/arch/analogdevices/dsp_abc9.ys

@@ -39,4 +39,3 @@ techmap -autoproc -wb -map +/analogdevices/cells_sim.v
 opt -full -fine
 select -assert-count 0 t:* t:$assert %d
 sat -verify -prove-asserts
-

tests/arch/common/blockram.v

@@ -325,4 +325,3 @@ module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
     );
 
 endmodule // double_sync_ram_tdp
-

tests/arch/common/memory_attributes/attributes_test.v

@@ -85,4 +85,3 @@ module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
 
    assign data_out = data_out_r;
 endmodule // distributed_ram
-

tests/arch/ecp5/add_sub.ys

@@ -9,4 +9,3 @@ select -assert-max 26 t:LUT4
 select -assert-count 10 t:PFUMX
 select -assert-count 6 t:L6MUX21
 select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D
-

tests/arch/ecp5/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
+select -assert-none t:TRELLIS_FF %% t:* %D

tests/arch/efinix/add_sub.ys

@@ -7,4 +7,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:EFX_ADD
 select -assert-count 4  t:EFX_LUT4
 select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
-

tests/arch/gowin/add_sub.ys

@@ -10,4 +10,3 @@ select -assert-count 8 t:IBUF
 select -assert-count 1 t:GND
 select -assert-count 1 t:VCC
 select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
-

tests/arch/gowin/compare.ys

@@ -5,5 +5,3 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 5 t:ALU
-
-

tests/arch/gowin/tribuf.ys

@@ -11,4 +11,4 @@ cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:TBUF
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:IBUF
-select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
+select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D

tests/arch/ice40/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:SB_LUT4
 select -assert-count 6 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
-

tests/arch/ice40/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFFE %% t:* %D
+select -assert-none t:SB_DFFE %% t:* %D

tests/arch/intel_alm/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 stat
 select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
-

tests/arch/intel_alm/adffs.ys

@@ -45,4 +45,3 @@ select -assert-count 1 t:MISTRAL_FF
 select -assert-count 2 t:MISTRAL_NOT
 
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
-

tests/arch/intel_alm/blockram.ys

@@ -5,4 +5,3 @@ cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D
-

tests/arch/intel_alm/counter.ys

@@ -10,4 +10,3 @@ select -assert-count 2 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/dffs.ys

@@ -18,4 +18,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/fsm.ys

@@ -19,4 +19,3 @@ select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
 select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/logic.ys

@@ -9,4 +9,3 @@ select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 6 t:MISTRAL_ALUT2
 select -assert-count 2 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
-

tests/arch/intel_alm/lutram.ys

@@ -37,4 +37,3 @@ select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
-

tests/arch/intel_alm/mul.ys

@@ -32,4 +32,3 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:MISTRAL_MUL27X27
 select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
-

tests/arch/intel_alm/mux.ys

@@ -42,4 +42,3 @@ select -assert-max 1 t:MISTRAL_ALUT3
 select -assert-max 2 t:MISTRAL_ALUT5
 select -assert-max 5 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/shifter.ys

@@ -7,4 +7,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/tribuf.ys

@@ -10,4 +10,3 @@ cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-

tests/arch/microchip/.gitignore

@@ -1,2 +1 @@
 *.vm
-

tests/arch/microchip/dff.ys

@@ -73,4 +73,4 @@ synth_microchip -top dffs -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CLKBUF
 select -assert-count 1 t:CFG1
-select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
+select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D

tests/arch/microchip/dff_opt.ys

@@ -39,4 +39,4 @@ synth_microchip -top dff_opt -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CFG4
 select -assert-count 1 t:CLKBUF
-select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D
+select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D

tests/arch/microchip/ram_SDP.ys

@@ -47,4 +47,4 @@ hierarchy -top sync_ram_sdp
 chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
 synth_microchip -top sync_ram_sdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/ram_TDP.ys

@@ -61,4 +61,4 @@ chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_tdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-count 2 t:CFG1
-select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D

tests/arch/microchip/reduce.ys

@@ -25,4 +25,3 @@ EOT
 synth_microchip -top reduce -family polarfire -noiopad
 select -assert-count 1 t:XOR8
 select -assert-none t:XOR8 %% t:* %D
-

tests/arch/microchip/simple_ram.ys

@@ -19,4 +19,4 @@ hierarchy -top sync_ram_sp
 chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_sp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/widemux.ys

@@ -38,4 +38,4 @@ equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 3 t:CFG3
-select -assert-none t:CFG3 %% t:* %D
+select -assert-none t:CFG3 %% t:* %D

tests/arch/xilinx/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_xilinx -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 1 t:RAMB18E1
-

tests/arch/xilinx/asym_ram_sdp_read_wider.v

@@ -69,4 +69,4 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 		end
 	end
 	assign doB = readB;
-endmodule
+endmodule

tests/arch/xilinx/asym_ram_sdp_write_wider.v

@@ -68,4 +68,4 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
 			end
 		end
 	end
-endmodule
+endmodule

tests/arch/xilinx/dffs.ys

@@ -42,4 +42,3 @@ cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
 select -assert-none t:BUFG t:FDRE %% t:* %D
-

tests/arch/xilinx/dsp_cascade.ys

@@ -87,4 +87,3 @@ select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)
 select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i
-

tests/arith_tree/arith_tree_alu_macc_equiv.ys

@@ -104,4 +104,4 @@ equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
-design -reset
+design -reset

tests/arith_tree/arith_tree_final_adder.ys

@@ -67,4 +67,3 @@ select -assert-none t:$add
 select -assert-min 1 t:$_AND_
 select -assert-min 1 t:$_XOR_
 design -reset
-

tests/asicworld/code_hdl_models_up_counter.v

@@ -26,4 +26,3 @@ end
 
 
 endmodule 
-

tests/asicworld/code_verilog_tutorial_counter_tb.v

@@ -98,4 +98,3 @@ if (count_compare != count) begin
 end
 
 endmodule
-

tests/bram/generate_mk.py

@@ -324,4 +324,3 @@ def create_tests():
                 )
 
 gen_tests_makefile.generate_custom(create_tests)
-

tests/errors/syntax_err01.v

@@ -1,4 +1,3 @@
 module a;
 integer [31:0]w;
 endmodule
-

tests/errors/syntax_err02.v

@@ -4,4 +4,3 @@ task to (
 );
 endtask
 endmodule
-

tests/errors/syntax_err03.v

@@ -4,4 +4,3 @@ task to (
 );
 endtask
 endmodule
-

tests/errors/syntax_err04.v

@@ -1,4 +1,3 @@
 module a;
 wire [3]x;
 endmodule
-

tests/errors/syntax_err05.v

@@ -1,4 +1,3 @@
 module a;
 input x[2:0];
 endmodule
-

tests/errors/syntax_err06.v

@@ -3,4 +3,3 @@ initial
 begin : label1
 end: label2
 endmodule
-

tests/errors/syntax_err07.v

@@ -3,4 +3,3 @@ wire [5:0]x;
 wire [3:0]y;
 assign y = (4)55;
 endmodule
-

tests/errors/syntax_err08.v

@@ -3,4 +3,3 @@ wire [5:0]x;
 wire [3:0]y;
 assign y = x 55;
 endmodule
-

tests/errors/syntax_err09.v

@@ -1,3 +1,2 @@
 module a(input wire x = 1'b0);
 endmodule
-

tests/errors/syntax_err13.v

@@ -1,4 +1,3 @@
 module a #(p = 0)
 ();
 endmodule
-

tests/functional/rtlil_cells.py

@@ -378,4 +378,4 @@ def generate_test_cases(per_cell, rnd):
                 names.append(f'{cell.name}-{name}' if name != '' else cell.name)
                 if per_cell is not None and len(seen_names) >= per_cell:
                     break
-    return (names, tests)
+    return (names, tests)

tests/functional/smt_vcd.py

@@ -185,4 +185,4 @@ def simulate_smt(smt_file_path, vcd_path, num_steps, rnd):
     try:
         simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd)
     finally:
-        smt_io.p_close()
+        smt_io.p_close()

tests/hana/README

@@ -1,4 +1,3 @@
 
 These test cases are copied from the hana project:
 https://sourceforge.net/projects/sim-sim/
-

tests/hana/hana_vlib.v

@@ -1136,4 +1136,3 @@ module INC64 #(parameter SIZE = 64) (input [SIZE-1:0] in, output [SIZE:0] out);
 assign out = in + 1;
 
 endmodule
-

tests/hana/test_simulation_decoder.v

@@ -216,4 +216,3 @@ always @(in or enable)
 	    endcase
 	end
 endmodule	
-

tests/hana/test_simulation_vlib.v

@@ -62,4 +62,3 @@ VCC synth_VCC_1(.out(
     synth_net_4));
 VCC synth_VCC_2(.out(synth_net_10));
 endmodule
-

tests/liberty/XNOR2X1.lib

@@ -334,4 +334,4 @@ library (ls05_stdcells) {
       }
     }
   }
-}
+}

tests/liberty/idranges.lib

@@ -3,4 +3,3 @@ library("foobar") {
     bar : baz[0] ;
   }
 }
-

tests/liberty/non-ascii.lib

@@ -11,4 +11,4 @@ library(dummy) {
       function : "A" ;
     }
   }
-}
+}

tests/liberty/retention.lib

@@ -54,4 +54,4 @@ library (retention) {
             direction : input;
         }
     }
-}
+}

tests/liberty/semicolmissing.lib

@@ -68,5 +68,3 @@ library(supergate) {
   }
 
 } /* end */
-
-

tests/memlib/generate_mk.py

@@ -1588,4 +1588,3 @@ extra = [
     "endif",
 ]
 gen_tests_makefile.generate_custom(create_tests, extra)
-

tests/memlib/memlib_lut.txt

@@ -25,4 +25,3 @@ ram distributed \RAM_LUT {
 		clock anyedge;
 	}
 }
-

tests/memlib/memlib_wide_write.v

@@ -26,4 +26,3 @@ always @(posedge PORT_A_CLK) begin
 end
 
 endmodule
-

tests/memories/amber23_sram_byte_en.v

@@ -81,4 +81,3 @@ always @(posedge i_clk)
     end
 
 endmodule
-

tests/memories/read_arst.v

@@ -24,4 +24,3 @@ always @(posedge clk, posedge reset) begin
 end
 
 endmodule
-

tests/memories/wide_read_async.v

@@ -24,4 +24,3 @@ always @(posedge clk) begin
 end
 
 endmodule
-

tests/memories/wide_read_mixed.v

@@ -43,4 +43,3 @@ always @(posedge clk) begin
 end
 
 endmodule
-

tests/memories/wide_read_sync.v

@@ -29,4 +29,3 @@ always @(posedge clk) begin
 end
 
 endmodule
-

tests/memories/wide_read_trans.v

@@ -37,4 +37,3 @@ always @(posedge clk) begin
 end
 
 endmodule
-

tests/opt/opt_dff_qd.ys

@@ -47,4 +47,3 @@ select -assert-count 6 t:$_DFFE_??_
 select -assert-count 4 t:$_DLATCH_?_
 select -assert-count 4 t:$_SR_??_
 select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
-

tests/opt/opt_dff_srst.ys

@@ -110,4 +110,3 @@ select -assert-count 2 t:$_DFF_P_
 select -assert-count 4 t:$_DFFE_PP_
 
 design -reset
-

tests/opt/opt_expr.ys

@@ -374,4 +374,4 @@ EOF
 
 scratchpad -set opt.did_something false
 opt_expr
-scratchpad -assert opt.did_something false
+scratchpad -assert opt.did_something false

tests/opt/opt_expr_mux_undef.ys

@@ -287,4 +287,3 @@ select -assert-none t:$_MUX16_
 select -assert-count 1 o:out %ci*
 
 ##########
-

tests/opt/opt_merge_properties.ys

@@ -13,4 +13,3 @@ chformal -lower
 clean
 opt_merge
 select -assert-count 2 t:$cover
-

tests/opt/opt_share_bug2538.ys

@@ -17,4 +17,3 @@ EOT
 proc
 alumacc
 equiv_opt -assert opt_share
-

tests/pyosys/test_sigspec_it.py

@@ -25,4 +25,3 @@ module = d.module(r"\spm")
 for conn_from, conn_to in module.connections_:
     for bit_from, bit_to in zip(conn_from, conn_to):
         print(f"assign {_dump_sigbit(bit_from)} = {_dump_sigbit(bit_to)};")
-

tests/rtlil/.gitignore

@@ -1 +1 @@
-/temp
+/temp

tests/sat/alu.v

@@ -76,4 +76,3 @@ module alu(
 		result <= tmp[7:0];
 	end
 endmodule
-

tests/sat/asserts_seq.v

@@ -84,4 +84,3 @@ module test_005(clk, a, a_old, b);
         assert(a_old != b);
     end
 endmodule
-

tests/sat/asserts_seq.ys

@@ -12,4 +12,3 @@ sat -falsify -prove-asserts -seq 2 test_002
 sat -falsify -prove-asserts -seq 2 test_003
 sat -falsify -prove-asserts -seq 2 test_004
 sat -verify  -prove-asserts -seq 2 test_005
-

tests/sat/counters-repeat.v

@@ -35,4 +35,3 @@ module counter2(clk, rst, ping);
 
 	assign ping = &count;
 endmodule
-

tests/sat/counters-repeat.ys

@@ -7,4 +7,3 @@ miter -equiv -make_assert -make_outputs counter1 counter2 miter
 
 cd miter; flatten; opt
 sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs
-

tests/sat/counters.v

@@ -32,4 +32,3 @@ module counter2(clk, rst, ping);
 
 	assign ping = &count;
 endmodule
-

tests/sat/counters.ys

@@ -7,4 +7,3 @@ miter -equiv -make_assert -make_outputs counter1 counter2 miter
 
 cd miter; flatten; opt
 sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs
-

tests/sat/expose_dff.v

@@ -30,4 +30,3 @@ always @(posedge clk, negedge rst_n)
 	else
 		y <= a != 0;
 endmodule
-

tests/sat/expose_dff.ys

@@ -12,4 +12,3 @@ flatten miter34; opt miter34
 
 sat -verify -prove trigger 0 miter12
 sat -verify -prove trigger 0 miter34
-

tests/sat/share.v

@@ -52,4 +52,3 @@ module test_3(
 		if (9 <= s && s < 12) y3 <= b / a;
 	end
 endmodule
-

tests/sdc/alu_sub.v

@@ -59,4 +59,3 @@ module alu(
 		result <= tmp[7:0];
 	end
 endmodule
-

tests/sdc/side-effects.sdc

@@ -1,2 +1,2 @@
 puts "This should print something:"
-puts [get_ports {A[0]}]
+puts [get_ports {A[0]}]

tests/sim/assume_x_first_step.ys

@@ -1,2 +1,2 @@
 read_verilog simple_assign.v
-sim -r simple_assign.vcd -scope simple_assign
+sim -r simple_assign.vcd -scope simple_assign

tests/sim/simple_assign.vcd

@@ -10,4 +10,4 @@ b1 n1
 b1 n2
 #10
 b0 n1
-b0 n2
+b0 n2

tests/sim/vcd_var_reference_whitespace.ys

@@ -1,3 +1,3 @@
 read_rtlil vector_assign.il
 sim -r var_reference_without_whitespace.vcd -scope tb.uut
-sim -r var_reference_with_whitespace.vcd -scope tb.uut
+sim -r var_reference_with_whitespace.vcd -scope tb.uut

tests/simple/aes_kexp128.v

@@ -21,4 +21,3 @@ always @(posedge clk) begin
 end
 
 endmodule
-

tests/simple/arraycells.v

@@ -12,4 +12,3 @@ module aoi12(a, b, c, y);
 	output y;
 	assign y = ~((a & b) | c);
 endmodule
-

tests/simple/attrib01_module.v

@@ -18,4 +18,3 @@ module attrib01_foo(clk, rst, inp, out);
 
   attrib01_bar bar_instance (clk, rst, inp, out);
 endmodule
-

tests/simple/attrib02_port_decl.v

@@ -22,4 +22,3 @@ module attrib02_foo(clk, rst, inp, out);
 
   attrib02_bar bar_instance (clk, rst, inp, out);
 endmodule
-