1059 commits

Author	SHA1	Message	Date
Pepijn de Vos	a3b25b4af8	Use -match-init to not synth contradicting init values	2019-12-03 15:12:25 +01:00
David Shah	e9ce4e658b	abc9: Fix breaking of SCCs ... Signed-off-by: David Shah <dave@ds0.me>	2019-12-01 20:44:56 +00:00
Eddie Hung	c61186dd9d	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-27 13:24:03 -08:00
Eddie Hung	ff1e357682	Add multiple driver testcase	2019-11-27 13:22:26 -08:00
Eddie Hung	4bac6b13be	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-27 10:17:10 -08:00
Eddie Hung	6464dc35ec	Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd ... xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder	2019-11-27 08:00:22 -08:00
Clifford Wolf	f43c0bd8ba	Merge pull request #1534 from YosysHQ/mwk/opt_share-fix ... opt_share: Fix handling of fine cells.	2019-11-27 11:23:16 +01:00
Eddie Hung	f6c0ec1d09	Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff	2019-11-27 01:03:33 -08:00
Eddie Hung	6338615aa1	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-27 01:02:16 -08:00
Eddie Hung	8c813632b6	Revert "submod to bitty rather bussy, for bussy wires used as input and output" ... This reverts commit cba3073026.	2019-11-27 00:48:22 -08:00
Eddie Hung	6318e3ce6d	Fix wire width	2019-11-26 23:38:49 -08:00
Eddie Hung	de3476cc23	No need for -abc9	2019-11-26 23:08:14 -08:00
Marcin Kościelnicki	fdcbda195b	opt_share: Fix handling of fine cells. ... Fixes #1525.	2019-11-27 08:01:07 +01:00
Eddie Hung	4a0198128e	Add citation	2019-11-26 22:51:16 -08:00
Eddie Hung	15042eaf57	Remove notes	2019-11-26 22:41:35 -08:00
Eddie Hung	222e199b73	Add testcase derived from fastfir_dynamictaps benchmark	2019-11-26 21:26:30 -08:00
Eddie Hung	dd317c9280	Add testcase where \init is copied	2019-11-25 16:07:35 -08:00
Eddie Hung	d087024caf	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-25 12:42:09 -08:00
Marcin Kościelnicki	6cdea425b8	clkbufmap: Add support for inverters in clock path.	2019-11-25 20:40:39 +01:00
Marcin Kościelnicki	7562e7304e	xilinx: Use INV instead of LUT1 when applicable	2019-11-25 20:40:39 +01:00
Pepijn de Vos	72d03dc910	attempt to fix formatting	2019-11-25 14:50:34 +01:00
Pepijn de Vos	6c79abbf5a	gowin: add and test dff init values	2019-11-25 14:33:21 +01:00
Eddie Hung	b46e636c91	Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff	2019-11-23 08:38:48 -08:00
Eddie Hung	d223e11a72	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 22:28:35 -08:00
Eddie Hung	5cd3d3db0a	Remove redundant flatten	2019-11-22 22:28:10 -08:00
Eddie Hung	08f85e6438	Stray dump	2019-11-22 20:53:48 -08:00
Eddie Hung	2c5dfd802d	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 17:24:45 -08:00
Eddie Hung	4fdcf8f7d7	Add another test with constant driver	2019-11-22 17:23:34 -08:00
Eddie Hung	74ea438136	Add testcase for signal used as part input part output	2019-11-22 16:52:55 -08:00
Eddie Hung	0806b8e398	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 16:50:56 -08:00
Eddie Hung	8779faf789	Cleanup spacing	2019-11-22 16:50:09 -08:00
Eddie Hung	2ef2e2c040	Add testcase	2019-11-22 16:48:11 -08:00
Eddie Hung	bd56161775	Merge branch 'eddie/clkpart' into xaig_dff	2019-11-22 15:38:48 -08:00
Eddie Hung	c761fa49b7	Missing endmodule	2019-11-22 12:37:57 -08:00
Clifford Wolf	72d2ef6fd0	Merge pull request #1511 from YosysHQ/dave/always ... sv: Error checking for always_comb, always_latch and always_ff	2019-11-22 15:32:29 +01:00
Marcin Kościelnicki	e110df9c48	gowin: Remove show command from tests.	2019-11-22 14:49:35 +01:00
Eddie Hung	6841e3b1c2	Another sloppy mistake!	2019-11-21 16:33:20 -08:00
Eddie Hung	fe36275234	Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff	2019-11-21 16:32:52 -08:00
Eddie Hung	39fdcb892b	async2sync -> clk2fflogic	2019-11-21 16:27:34 -08:00
Eddie Hung	5a30e3ac3b	Merge branch 'eddie/xaig_dff_adff' into xaig_dff	2019-11-21 16:15:25 -08:00
Eddie Hung	911a152b39	Add test	2019-11-21 16:13:28 -08:00
David Shah	49b670ca38	sv: Add tests for SV always types ... Signed-off-by: David Shah <dave@ds0.me>	2019-11-21 21:06:28 +00:00
Eddie Hung	cd9e830b67	Add multi clock test	2019-11-20 13:28:55 -08:00
Eddie Hung	1cc106452f	Add a equiv test too	2019-11-19 17:05:14 -08:00
Eddie Hung	90c5ca330c	Add two tests	2019-11-19 16:57:58 -08:00
Clifford Wolf	7ea0a5937b	Merge pull request #1449 from pepijndevos/gowin ... Improvements for gowin support	2019-11-19 17:29:27 +01:00
Marcin Kościelnicki	15232a48af	Fix #1462, #1480.	2019-11-19 08:57:39 +01:00
Marcin Kościelnicki	38e72d6e13	Fix #1496.	2019-11-18 04:16:48 +01:00
Pepijn de Vos	32f0296df1	Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin	2019-11-16 12:43:17 +01:00
Pepijn de Vos	ab8c521030	fix fsm test with proper clock enable polarity	2019-11-11 17:51:26 +01:00