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xilinx: Use INV instead of LUT1 when applicable
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5 changed files with 14 additions and 10 deletions
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@ -20,9 +20,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDCE
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:INV
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select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
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select -assert-none t:BUFG t:FDCE t:INV %% t:* %D
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design -load read
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@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDCE
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:INV
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select -assert-count 7 t:MUXCY
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select -assert-count 8 t:XORCY
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select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D
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select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
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@ -18,9 +18,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalen
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LDCE
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:INV
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select -assert-none t:LDCE t:LUT1 %% t:* %D
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select -assert-none t:LDCE t:INV %% t:* %D
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design -load read
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@ -5,7 +5,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 1 t:INV
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select -assert-count 6 t:LUT2
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select -assert-count 2 t:LUT4
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select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
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select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D
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