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read_verilog <<EOT
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// Citation https://github.com/ZipCPU/dspfilters/blob/master/rtl/fastfir.v
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module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
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wire [30:0] _00_;
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wire [23:0] _01_;
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