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Eddie Hung 2019-11-26 22:51:16 -08:00
parent 2105ae176a
commit 4a0198128e
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tests/arch/xilinx/dsp_fastfir.ys
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@ -1,4 +1,5 @@
read_verilog <<EOT
// Citation https://github.com/ZipCPU/dspfilters/blob/master/rtl/fastfir.v
module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
wire [30:0] _00_;
wire [23:0] _01_;