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https://github.com/YosysHQ/yosys
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attempt to fix formatting
This commit is contained in:
Pepijn de Vos
parent
6c79abbf5a
commit
72d03dc910
2 changed files with 292 additions and 292 deletions
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@ -6,108 +6,108 @@ module myDFF (output reg Q, input CLK, D);
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endmodule
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module myDFFE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFE (positive clock edge; clock enable)
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module myDFFS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFS (positive clock edge; synchronous set)
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module myDFFSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
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module myDFFR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFR (positive clock edge; synchronous reset)
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module myDFFRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
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module myDFFP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFP (positive clock edge; asynchronous preset)
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module myDFFPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
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module myDFFC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFC (positive clock edge; asynchronous clear)
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module myDFFCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
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@ -119,106 +119,106 @@ module myDFFN (output reg Q, input CLK, D);
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endmodule
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module myDFFNE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFNE (negative clock edge; clock enable)
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module myDFFNS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNS (negative clock edge; synchronous set)
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module myDFFNSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
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module myDFFNR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNR (negative clock edge; synchronous reset)
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module myDFFNRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
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module myDFFNP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNP (negative clock edge; asynchronous preset)
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module myDFFNPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
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module myDFFNC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNC (negative clock edge; asynchronous clear)
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module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
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