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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

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Eddie Hung 2019-11-27 01:02:16 -08:00
commit 6338615aa1
2 changed files with 94 additions and 49 deletions
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25
tests/various/submod.ys
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@ -1,8 +1,8 @@
read_verilog <<EOT
module top(input a, output [1:0] b);
module top(input a, output b);
wire c;
(* submod="bar" *) sub s1(a, c);
assign b[0] = c;
assign b = c;
endmodule
module sub(input a, output c);
@ -48,3 +48,24 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
DFF s2(.D(d), .C(c), .Q(q[0]));
DFF s3(.D(d), .C(c), .Q(q[2]));
endmodule
module DFF(input D, C, output Q);
parameter INIT = 1'b0;
endmodule
EOT
hierarchy -top top
proc
submod
dffinit -ff DFF Q INIT
check -noinit -assert