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https://github.com/YosysHQ/yosys
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clkbufmap: Add support for inverters in clock path.
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parent
7562e7304e
commit
6cdea425b8
4 changed files with 69 additions and 6 deletions
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@ -4,6 +4,7 @@ module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
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module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
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module latch (input e, d, output q); endmodule
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module clkgen (output o); endmodule
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module inv ((* clkbuf_inv = "i" *) output o, input i); endmodule
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module top(input clk1, clk2, clk3, d, e, output [4:0] q);
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wire clk4, clk5, clk6;
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@ -17,12 +18,18 @@ dff s6 (.clk(clk6), .d(d), .q(q[4]));
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endmodule
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module sub(output sclk4, output sclk5, output sclk6, input sd, output sq);
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wire sclk7, sclk8, sclk9;
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wire siq;
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wire tmp;
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clkgen s7(.o(sclk4));
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clkgen s8(.o(sclk5));
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clkgen s9(.o(tmp));
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clkbuf s10(.i(tmp), .o(sclk6));
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dff s11(.clk(sclk4), .d(sd), .q(sq));
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clkbuf s10(.i(tmp), .o(sclk7));
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dff s11(.clk(sclk4), .d(sd), .q(siq));
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inv s15(.i(sclk7), .o(sclk6));
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clkgen s12(.o(sclk8));
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inv s13(.o(sclk9), .i(sclk8));
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dff s14(.clk(sclk9), .d(siq), .q(sq));
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endmodule
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EOT
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@ -34,7 +41,7 @@ design -save ref
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design -load ref
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clkbufmap -buf clkbuf o:i
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select -assert-count 3 top/t:clkbuf
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select -assert-count 2 sub/t:clkbuf
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select -assert-count 3 sub/t:clkbuf
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select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
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select -assert-count 1 @clk1 # Check there is one such fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
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@ -51,6 +58,10 @@ select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
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select -assert-count 1 @sclk4
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select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
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select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i
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select -set sclk8 w:sclk8 %a %ci t:clkbuf %i
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select -assert-count 1 @sclk8
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select -assert-count 1 @sclk8 %x:+[o] %co c:s13 %i
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select -assert-count 1 @sclk8 %x:+[i] %ci c:s12 %i
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# ----------------------
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@ -72,7 +83,7 @@ setattr -set clkbuf_inhibit 1 w:clk1
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setattr -set buffer_type "bufg" w:clk2
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clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 3 top/t:clkbuf
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select -assert-count 2 sub/t:clkbuf
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select -assert-count 3 sub/t:clkbuf
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select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
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select -assert-count 1 @clk1 # Check there is one such fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
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@ -93,4 +104,4 @@ clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 0 w:clk1 %a %co t:clkbuf %i
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select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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select -assert-count 0 top/t:clkbuf
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select -assert-count 1 sub/t:clkbuf
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select -assert-count 2 sub/t:clkbuf
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