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This commit is contained in:
Eddie Hung 2019-11-21 16:13:28 -08:00
parent a576747483
commit 911a152b39

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@ -268,7 +268,12 @@ assign o = { 1'b1, 1'bx };
assign p = { 1'b1, 1'bx, 1'b0 };
endmodule
module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
module abc9_test029(input clk1, clk2, d, output reg q1, q2);
always @(posedge clk1) q1 <= d;
always @(negedge clk2) q2 <= q1;
endmodule
module abc9_test030(input clk, d, output reg q1, q2);
always @(posedge clk) q1 <= d;
always @(posedge clk) q2 <= q1;
endmodule