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Add testcase where \init is copied

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This commit is contained in:
Eddie Hung 2019-11-25 16:07:35 -08:00
parent 5cd3d3db0a
commit dd317c9280
1 changed files with 18 additions and 0 deletions
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18
tests/various/submod.ys
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@ -48,3 +48,21 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module top(input d, c, (* init = 1'b1 *) output reg q);
(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q));
endmodule
module DFF(input D, C, output Q);
parameter INIT = 1'b0;
endmodule
EOT
hierarchy -top top
submod
dffinit -ff DFF Q INIT
check -noinit -assert