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2 changed files with 24 additions and 4 deletions
13
tests/opt/bug1525.ys
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13
tests/opt/bug1525.ys
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@ -0,0 +1,13 @@
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read_verilog << EOF
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module top(...);
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input A1, A2, B, S;
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output O;
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assign O = S ? (A1 & B) : (A2 & B);
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endmodule
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EOF
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simplemap
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opt_share
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dump
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