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Add multiple driver testcase

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This commit is contained in:
Eddie Hung 2019-11-27 13:22:26 -08:00
parent 1c0ee4f786
commit ff1e357682
1 changed files with 31 additions and 0 deletions
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31
tests/various/submod.ys
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@ -15,6 +15,7 @@ proc
design -save gold
submod
check -assert
design -stash gate
design -import gold -as gold
@ -41,6 +42,7 @@ proc
design -save gold
submod
check -assert top
design -stash gate
design -import gold -as gold
@ -50,6 +52,35 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog <<EOT
module top(input a, output [1:0] b, c);
(* submod="bar" *) sub s1(a, b[0]);
(* submod="bar" *) sub s2(a, c[1]);
assign c = b;
endmodule
module sub(input a, output c);
assign c = a;
endmodule
EOT
hierarchy -top top
proc
design -save gold
submod
check -assert top
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);