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Fix wire width

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This commit is contained in:
Eddie Hung 2019-11-26 23:38:49 -08:00
parent 5e487b103c
commit 6318e3ce6d
1 changed files with 2 additions and 2 deletions
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4
tests/various/submod.ys
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@ -1,8 +1,8 @@
read_verilog <<EOT
module top(input a, output [1:0] b);
module top(input a, output b);
wire c;
(* submod="bar" *) sub s1(a, c);
assign b[0] = c;
assign b = c;
endmodule
module sub(input a, output c);