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fix fsm test with proper clock enable polarity

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Pepijn de Vos 2019-11-11 17:51:26 +01:00
parent ec3faa7b96
commit ab8c521030
2 changed files with 15 additions and 4 deletions
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tests/arch/gowin/fsm.ys Normal file
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read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check
miter -equiv -make_assert -flatten gold gate miter
sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
#design -load postopt
#shell