Eddie Hung 6464dc35ec Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd ... xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder		2019-11-27 08:00:22 -08:00
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aiger
arch	No need for -abc9	2019-11-26 23:08:14 -08:00
asicworld
bram
errors
fsm
hana
liberty
lut
memories
opt	opt_share: Fix handling of fine cells.	2019-11-27 08:01:07 +01:00
opt_share
proc
realmath
rpc	rpc: new frontend.	2019-09-30 15:53:11 +00:00
sat	Revert "Add test that is expecting to fail"	2019-10-08 12:41:26 -07:00
share
simple
simple_abc9	Remove notes	2019-11-26 22:41:35 -08:00
smv
sva
svinterfaces
svtypes	Use "(id)" instead of "id" for types as temporary hack	2019-10-14 05:24:31 +02:00
techmap	clkbufmap: Add support for inverters in clock path.	2019-11-25 20:40:39 +01:00
tools
unit
various	sv: Add tests for SV always types	2019-11-21 21:06:28 +00:00
vloghtb