3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 01:54:10 +00:00

Add testcase for signal used as part input part output

This commit is contained in:
Eddie Hung 2019-11-22 16:52:55 -08:00
parent 81548d1ef9
commit 74ea438136

View file

@ -289,3 +289,8 @@ module abc9_test033(input clk, d, output reg q1, q2);
always @(posedge clk) q1 <= d;
always @(posedge clk) q2 <= q1;
endmodule
module abc9_test034(input clk, d, output reg [1:0] q);
always @(posedge clk) q[0] <= d;
always @(negedge clk) q[1] <= q[0];
endmodule