Merge branch 'eddie/xaig_dff_adff' into xaig_dff

tests/simple_abc9/abc9.v

@@ -268,12 +268,23 @@ assign o = { 1'b1, 1'bx };
 assign p = { 1'b1, 1'bx, 1'b0 };
 endmodule
 
-module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+module abc9_test029(input clk, d, r, output reg q);
+always @(posedge clk or posedge r)
+    if (r) q <= 1'b0;
+    else q <= d;
+endmodule
+
+module abc9_test030(input clk, d, r, output reg q);
+always @(negedge clk or posedge r)
+    if (r) q <= 1'b1;
+    else q <= d;
+endmodule
+
+module abc9_test032(input clk1, clk2, d, output reg q1, q2);
 always @(posedge clk1) q1 <= d;
 always @(negedge clk2) q2 <= q1;
 endmodule
 
-module abc9_test030(input clk, d, output reg q1, q2);
+module abc9_test033(input clk, d, output reg q1, q2);
 always @(posedge clk) q1 <= d;
 always @(posedge clk) q2 <= q1;
-endmodule

tests/various/abc9.v

@@ -9,3 +9,10 @@ wire w;
 unknown u(~i, w);
 unknown2 u2(w, o);
 endmodule
+
+module abc9_test031(input clk, d, r, output reg q);
+initial q = 1'b0;
+always @(negedge clk or negedge r)
+    if (r) q <= 1'b0;
+    else q <= d;
+endmodule

tests/various/abc9.ys

@@ -22,3 +22,19 @@ abc9 -lut 4
 select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
 select -assert-count 1 t:unknown
 select -assert-none t:$lut t:unknown %% t: %D
+
+design -load read
+hierarchy -top abc9_test031
+proc
+async2sync
+design -save gold
+
+abc9 -lut 4
+check
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 10 -verify -prove-asserts -show-ports miter