Akash Levy
6e88c689f2
Merge branch 'YosysHQ:main' into main
2024-12-01 12:32:07 -05:00
Emil J. Tywoniak
3ebc714dbc
techmap: test consistently with other equiv_make tests
2024-11-29 00:15:02 +01:00
Emil J. Tywoniak
91844968fd
techmap: wrap builtin $lcu as golden module in PPA tests
2024-11-29 00:13:21 +01:00
Emil J. Tywoniak
a41ef0271c
techmap: remove ppa.nomatch by purging internal signals
2024-11-29 00:03:49 +01:00
Emil J. Tywoniak
4bf3677640
techmap: set Han-Carlson adder priority consistent with Kogge-Stone
2024-11-28 23:54:00 +01:00
Emil J. Tywoniak
3f078d9afa
tests: rework Kogge-Stone test consistently with Han-Carlson
2024-11-28 15:33:21 +01:00
Emil J. Tywoniak
1a562f9605
techmap: add TCL test for Han-Carlson adder
2024-11-28 15:33:21 +01:00
Emil J. Tywoniak
289673a807
tests: add support for tcl tests
2024-11-28 15:33:21 +01:00
Miodrag Milanović
29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific
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verific: fix blackbox regression and add test case
2024-11-25 15:06:54 +01:00
Akash Levy
f855b39dbb
Merge branch 'YosysHQ:main' into main
2024-11-21 00:34:49 -08:00
Emil J
5b6baa3ef1
Merge pull request #4744 from YosysHQ/emil/clockgate-liberty
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clockgate: add -liberty
2024-11-20 15:04:00 +01:00
George Rennie
9043dc0ad6
tests: replace read_ilang with read_rtlil
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* #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil
2024-11-20 14:54:23 +01:00
Emil J
cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width
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opt_demorgan: skip zero width cells
2024-11-20 13:33:16 +01:00
Emil J
18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width
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opt_reduce: keep at least one input to $reduce_or/and cells
2024-11-20 13:33:04 +01:00
Martin Povišer
7ebe451f9a
Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs
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proc_dff: fix early return bug
2024-11-20 13:26:32 +01:00
Akash Levy
5eaf627645
Undo Liberty stuff
2024-11-18 17:10:25 -08:00
Akash Levy
1a69c51c88
Merge branch 'YosysHQ:main' into main
2024-11-18 16:10:30 -08:00
Martin Povišer
270846a49a
Merge pull request #4723 from povik/memv2-nordports
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rtlil: Adjust internal check for `$mem_v2` cells
2024-11-18 15:44:39 +01:00
Emil J. Tywoniak
a5bc36f77e
clockgate: add -dont_use
2024-11-18 13:45:30 +01:00
Emil J. Tywoniak
b08441d95c
clockgate: shuffle test liberty to exercise comparison better
2024-11-18 12:48:50 +01:00
Emil J. Tywoniak
1e3f8cc630
clockgate: add test liberty file
2024-11-18 12:45:27 +01:00
Emil J. Tywoniak
c921d85a85
clockgate: fix test comments
2024-11-18 12:33:09 +01:00
Akash Levy
3190771892
Small fixes to get a test working
2024-11-16 22:21:58 -08:00
Akash Levy
df0ce40841
blif fixes
2024-11-16 21:53:06 -08:00
Martin Povišer
0d5c412807
read_liberty: s/busses/buses/
2024-11-12 13:33:41 +01:00
Martin Povišer
56a9202a97
Add read_liberty tests of new options
2024-11-12 13:29:16 +01:00
Martin Povišer
5a0cb5d453
Check in filtered samples of IHP's Liberty data for tests
2024-11-12 13:28:15 +01:00
Akash Levy
1017b19405
Small README updates
2024-11-12 02:53:13 -08:00
Akash Levy
ea76abdaee
Merge
2024-11-11 11:47:58 -08:00
Martin Povišer
1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate
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peepopt: Add formal opt to rewrite latches to ffs in clock gates
2024-11-11 14:49:09 +01:00
Akash Levy
fa50434708
Merge branch 'YosysHQ:main' into main
2024-11-08 14:10:24 -08:00
Martin Povišer
e82e5f8b13
rtlil: Adjust internal check for $mem_v2 cells
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There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.
The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.
Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.
This breaks RTLIL compatibility but for an obscure edge case.
2024-11-08 15:18:43 +01:00
Miodrag Milanovic
df391f5816
verific: fix blackbox regression and add test case
2024-11-08 14:57:04 +01:00
KrystalDelusion
4343c791cb
Merge pull request #4704 from YosysHQ/krys/drop_ilang
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Remove references to ilang
2024-11-08 11:28:06 +13:00
Akash Levy
0e3adb38fc
Merge branch 'YosysHQ:main' into main
2024-11-07 11:24:11 -08:00
George Rennie
a31c968340
tests/bufnorm: add test for bufnorm of constant
2024-11-07 12:55:50 +01:00
George Rennie
c23e64a236
tests/proc: add proc_dff bug 4712 as testcase
2024-11-07 00:10:17 +01:00
Akash Levy
37914ff129
Merge branch 'YosysHQ:main' into main
2024-11-06 14:14:08 -08:00
N. Engelhardt
2de9f00368
Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing
2024-11-06 16:29:07 +01:00
N. Engelhardt
9068ec5566
Merge pull request #4627 from RCoeurjoly/roland/assume_x
2024-11-06 16:27:30 +01:00
Akash Levy
c2f95d1b5a
Add more Liberty tests and fix parentheses in functions
2024-11-05 10:34:51 -08:00
Akash Levy
1cba744712
Update
2024-11-04 17:01:41 -08:00
Krystine Sherwin
ee73a91f44
Remove references to ilang
2024-11-05 12:36:31 +13:00
Lofty
3250f2b82b
Merge pull request #4700 from povik/select-list-mod
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Add `select -list-mod`
2024-11-04 15:38:42 +00:00
Martin Povišer
d752ca4847
Fix test after option change
2024-11-04 16:26:46 +01:00
Martin Povišer
c9ed6d8dcf
cellmatch: Rename -lut_attrs to -derive_luts; document option
2024-11-04 14:28:40 +01:00
Martin Povišer
7aa3fdab80
select: Add -list-mod option
2024-11-04 13:16:13 +01:00
Akash Levy
711e1f3164
Merge branch 'YosysHQ:main' into main
2024-10-16 13:21:03 -07:00
Martin Povišer
9432e972f7
Merge pull request #4626 from povik/select-t-at
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select: Add new `t:@<name>` syntax
2024-10-16 10:18:05 +02:00
Emil J. Tywoniak
f9f509bc25
select: add t:@<name> test
2024-10-15 21:06:06 +02:00
