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tests/bufnorm: add test for bufnorm of constant

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George Rennie 2024-11-07 12:55:50 +01:00
parent 8f6058a7d6
commit a31c968340
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# Check wires driven by constants are kept
read_verilog <<EOT
module top(output wire [7:0] y);
assign y = 27;
endmodule
EOT
equiv_opt -assert bufnorm
design -load postopt
select -assert-count 1 t:$buf
select -assert-count 1 w:y %ci t:$buf %i