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This commit is contained in:
Akash Levy 2024-11-04 17:01:41 -08:00
commit 1cba744712
10 changed files with 68 additions and 27 deletions
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2
Makefile
View file

@ -162,7 +162,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
YOSYS_VER := 0.46+135
YOSYS_VER := 0.46+147
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo

25
frontends/ast/ast.cc
View file

@ -877,16 +877,25 @@ AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
// create an AST node for a constant (using a string as value)
AstNode *AstNode::mkconst_str(const std::string &str)
{
std::vector<RTLIL::State> data;
data.reserve(str.size() * 8);
for (size_t i = 0; i < str.size(); i++) {
unsigned char ch = str[str.size() - i - 1];
for (int j = 0; j < 8; j++) {
data.push_back((ch & 1) ? State::S1 : State::S0);
ch = ch >> 1;
AstNode *node;
// LRM 1364-2005 5.2.3.3 The empty string literal ("") shall be considered
// equivalent to the ASCII NUL ("\0")
if (str.empty()) {
node = AstNode::mkconst_int(0, false, 8);
} else {
std::vector<RTLIL::State> data;
data.reserve(str.size() * 8);
for (size_t i = 0; i < str.size(); i++) {
unsigned char ch = str[str.size() - i - 1];
for (int j = 0; j < 8; j++) {
data.push_back((ch & 1) ? State::S1 : State::S0);
ch = ch >> 1;
}
}
node = AstNode::mkconst_bits(data, false);
}
AstNode *node = AstNode::mkconst_bits(data, false);
node->is_string = true;
node->str = str;
return node;

8
kernel/yosys.cc
View file

@ -549,10 +549,6 @@ void yosys_setup()
return;
already_setup = true;
#define X(_id) RTLIL::ID::_id = "\\" # _id;
#include "kernel/constids.inc"
#undef X
#ifdef WITH_PYTHON
// With Python 3.12, calling PyImport_AppendInittab on an already
// initialized platform fails (such as when libyosys is imported
@ -568,6 +564,10 @@ void yosys_setup()
init_share_dirname();
init_abc_executable_name();
#define X(_id) RTLIL::ID::_id = "\\" # _id;
#include "kernel/constids.inc"
#undef X
Pass::init_register();
yosys_design = new RTLIL::Design;
yosys_celltypes.setup();

3
passes/cmds/logger.cc
View file

@ -162,7 +162,8 @@ struct LoggerPass : public Pass {
log_cmd_error("Number of expected messages must be higher then 0 !\n");
if (type=="error" && count!=1)
log_cmd_error("Expected error message occurrences must be 1 !\n");
log("Added regex '%s' for warnings to expected %s list.\n", pattern.c_str(), type.c_str());
log("Added regex '%s' to expected %s messages list.\n",
pattern.c_str(), type.c_str());
try {
if (type == "error")
log_expect_error[pattern] = LogExpectedItem(YS_REGEX_COMPILE(pattern), count);

12
passes/cmds/select.cc
View file

@ -1041,7 +1041,7 @@ struct SelectPass : public Pass {
log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
log(" select [ -unset <name> ]\n");
log(" select [ <assert_option> ] {-read <filename> | <selection>}\n");
log(" select [ -list | -write <filename> | -count | -clear ]\n");
log(" select [ -list | -list-mod | -write <filename> | -count | -clear ]\n");
log(" select -module <modname>\n");
log("\n");
log("Most commands use the list of currently selected objects to determine which part\n");
@ -1277,6 +1277,7 @@ struct SelectPass : public Pass {
bool clear_mode = false;
bool none_mode = false;
bool list_mode = false;
bool list_mod_mode = false;
bool count_mode = false;
bool got_module = false;
bool assert_none = false;
@ -1338,6 +1339,11 @@ struct SelectPass : public Pass {
list_mode = true;
continue;
}
if (arg == "-list-mod") {
list_mode = true;
list_mod_mode = true;
continue;
}
if (arg == "-write" && argidx+1 < args.size()) {
write_file = args[++argidx];
continue;
@ -1416,7 +1422,7 @@ struct SelectPass : public Pass {
log_cmd_error("Options %s can not be combined.\n", common_flagset);
if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
log_cmd_error("Options -list, -write and -count can not be combined with %s.\n", common_flagset);
log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset);
if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || !unset_name.empty() || common_flagset_tally))
log_cmd_error("Option -set can not be combined with -list, -write, -count, -unset, %s.\n", common_flagset);
@ -1467,7 +1473,7 @@ struct SelectPass : public Pass {
{
if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name));
if (sel->selected_module(mod->name)) {
if (sel->selected_module(mod->name) && !list_mod_mode) {
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name))

20
passes/techmap/cellmatch.cc
View file

@ -155,18 +155,22 @@ struct CellmatchPass : Pass {
log("equivalent as long as their truth tables are identical upto a permutation of\n");
log("inputs and outputs. The supported number of inputs is limited to 6.\n");
log("\n");
log(" cellmatch -derive_luts [module selection]\n");
log("\n");
log("For every port in each selected module, characterize its combinational\n");
log("function with a 'lut' attribute if possible.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *d) override
{
log_header(d, "Executing CELLMATCH pass. (match cells)\n");
size_t argidx;
bool lut_attrs = false;
bool derive_luts = false;
Design *lib = NULL;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-lut_attrs") {
// an undocumented debugging option
lut_attrs = true;
if (args[argidx] == "-derive_luts") {
derive_luts = true;
} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
if (!saved_designs.count(args[++argidx]))
log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
@ -177,8 +181,8 @@ struct CellmatchPass : Pass {
}
extra_args(args, argidx, d);
if (!lib && !lut_attrs)
log_cmd_error("Missing required -lib option.\n");
if (!lib && !derive_luts)
log_cmd_error("Missing required -lib or -derive_luts option.\n");
struct Target {
Module *module;
@ -210,7 +214,7 @@ struct CellmatchPass : Pass {
r.first->second = new Design;
Design *map_design = r.first->second;
for (auto m : d->selected_whole_modules_warn()) {
for (auto m : d->selected_whole_modules_warn(/* visit whiteboxes */derive_luts)) {
std::vector<uint64_t> luts;
if (!derive_module_luts(m, luts))
continue;
@ -218,7 +222,7 @@ struct CellmatchPass : Pass {
SigSpec inputs = module_inputs(m);
SigSpec outputs = module_outputs(m);
if (lut_attrs) {
if (derive_luts) {
int no = 0;
for (auto bit : outputs) {
log_assert(bit.is_wire());

2
setup.py
View file

@ -76,7 +76,7 @@ class libyosys_so_ext(Extension):
# yosys-abc
yosys_abc_target = os.path.join(pyosys_path, "yosys-abc")
shutil.copy("yosys-abc", yosys_abc_target)
bext.spawn(["strip", "-S", "yosys-abc"])
bext.spawn(["strip", "-S", yosys_abc_target])
# share directory
share_target = os.path.join(pyosys_path, "share")

13
tests/select/list_mod.ys Normal file
View file

@ -0,0 +1,13 @@
read_verilog <<EOF
module top1;
(* foo *)
wire w;
endmodule
module top2;
(* bar *)
wire w;
endmodule
EOF
logger -expect log top1 1
select -list-mod a:foo %m

2
tests/select/mod-attribute.ys
View file

@ -41,7 +41,7 @@ module \top
end
EOT
cellmatch -lut_attrs *
cellmatch -derive_luts *
select -set buffers a:lut=2'b10 %m
select -set inverters a:lut=2'b01 %m

8
tests/techmap/cellmatch.ys
View file

@ -77,3 +77,11 @@ opt_clean
equiv_induct equiv
equiv_status -assert
design -reset
design -load gatelib
cellmatch -derive_luts
select -assert-any bufgate/w:Y a:lut=2'b10 %i
select -assert-any reducegate/w:X a:lut=8'b10000000 %i
select -assert-any reducegate/w:Y a:lut=8'b11111110 %i
select -assert-any fagate/w:X a:lut=8'b10010110 %i
select -assert-any fagate/w:Y a:lut=8'b11101000 %i