Update

tests/select/list_mod.ys

@@ -0,0 +1,13 @@
+read_verilog <<EOF
+module top1;
+(* foo *)
+wire w;
+endmodule
+
+module top2;
+(* bar *)
+wire w;
+endmodule
+EOF
+logger -expect log top1 1
+select -list-mod a:foo %m

tests/select/mod-attribute.ys

@@ -41,7 +41,7 @@ module \top
 end
 EOT
 
-cellmatch -lut_attrs *
+cellmatch -derive_luts *
 
 select -set buffers a:lut=2'b10 %m
 select -set inverters a:lut=2'b01 %m

tests/techmap/cellmatch.ys

@@ -77,3 +77,11 @@ opt_clean
 equiv_induct equiv
 equiv_status -assert
 
+design -reset
+design -load gatelib
+cellmatch -derive_luts
+select -assert-any bufgate/w:Y a:lut=2'b10 %i
+select -assert-any reducegate/w:X a:lut=8'b10000000 %i
+select -assert-any reducegate/w:Y a:lut=8'b11111110 %i
+select -assert-any fagate/w:X a:lut=8'b10010110 %i
+select -assert-any fagate/w:Y a:lut=8'b11101000 %i