Merge branch 'YosysHQ:main' into main

tests/arch/ecp5/bug1630.ys

@@ -1,2 +1,2 @@
-read_ilang bug1630.il.gz
+read_rtlil bug1630.il.gz
 abc9 -lut 4

tests/arch/ecp5/opt_lut_ins.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 
 module \top
 

tests/arch/ice40/bug1626.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 # Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os)
 autoidx 2815
 attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9"

tests/arch/ice40/bug1644.ys

@@ -1,2 +1,2 @@
-read_ilang bug1644.il.gz
+read_rtlil bug1644.il.gz
 synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram

tests/arch/xilinx/opt_lut_ins.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 
 module \top
 

tests/opt/bug2920.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 
 module \mod
   wire input 1 \clk

tests/opt/memory_bmux2rom.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 4 input 0 \S

tests/opt/opt_lut_elim.ys

@@ -1,3 +1,3 @@
-read_ilang opt_lut_elim.il
+read_rtlil opt_lut_elim.il
 opt_lut
 select -assert-count 0 t:$lut

tests/opt/opt_lut_ins.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 
 module \top
 

tests/opt/opt_lut_port.ys

@@ -1,3 +1,3 @@
-read_ilang opt_lut_port.il
+read_rtlil opt_lut_port.il
 opt_lut
 select -assert-count 2 t:$lut

tests/opt/opt_reduce_bmux.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 12 input 0 \A
@@ -22,7 +22,7 @@ select -assert-count 1 t:$bmux r:WIDTH=4 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 6 input 0 \A
@@ -46,7 +46,7 @@ select -assert-count 0 t:$bmux
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 160 input 0 \A
@@ -70,7 +70,7 @@ select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 10 input 0 \A
@@ -95,7 +95,7 @@ select -assert-count 1 t:$mux
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 5 input 0 \A

tests/opt/opt_reduce_demux.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 4 input 0 \A
@@ -22,7 +22,7 @@ select -assert-count 1 t:$demux r:WIDTH=4 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 2 input 1 \S
@@ -45,7 +45,7 @@ select -assert-count 0 t:$demux
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 5 input 0 \A
@@ -69,7 +69,7 @@ select -assert-count 1 t:$demux r:S_WIDTH=2 %i
 
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 5 input 0 \A

tests/proc/bug2962.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 module \top
    wire width 4 input 1 \a
    wire width 2 input 2 \b

tests/proc/proc_rom.ys

@@ -188,7 +188,7 @@ equiv_opt -assert -run prepare: dummy
 
 design -reset
 
-read_ilang <<EOT
+read_rtlil <<EOT
 
 module \m
   wire width 3 input 1 \a

tests/rpc/frontend.py

@@ -5,7 +5,7 @@ def derive(module, parameters):
 	assert module == r"python_inv"
 	if parameters.keys() != {r"\width"}:
 		raise ValueError("Invalid parameters")
-	return "ilang", r"""
+	return "rtlil", r"""
 module \impl
 	wire width {width:d} input 1 \i
 	wire width {width:d} output 2 \o

tests/sat/bug2595.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 module \top
   wire input 3 \A
   wire width 2 input 2 \B

tests/smv/run-single.sh

@@ -8,7 +8,7 @@ EOT
 cat > $1.ys <<EOT
 echo on
 
-read_ilang $1.il
+read_rtlil $1.il
 hierarchy; proc; opt
 rename -top uut
 design -save gold

tests/techmap/bmuxmap_pmux.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 4 input 0 \S
@@ -21,7 +21,7 @@ equiv_opt -assert bmuxmap -pmux
 ###
 design -reset
 
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire width 10 input 0 \A

tests/various/autoname.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 autoidx 2
 module \top
   wire output 3 $y

tests/various/bug1496.ys

@@ -1,4 +1,4 @@
-read_ilang << EOF
+read_rtlil << EOF
 module \top
   wire input 1 \A
   wire output 2 \Y

tests/various/equiv_opt_undef.ys

@@ -1,4 +1,4 @@
-read_ilang << EOT
+read_rtlil << EOT
 
 module \top
   wire $a

tests/verilog/assign_to_reg.ys

@@ -1,6 +1,6 @@
 # https://github.com/yosyshq/yosys/issues/2035
 
-read_ilang <<END
+read_rtlil <<END
 module \top
   wire width 1 input 0 \halfbrite
   wire width 2 output 1 \r_on