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Merge branch 'YosysHQ:main' into main

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Akash Levy 2024-11-07 11:24:11 -08:00 • committed by GitHub
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# Check wires driven by constants are kept
read_verilog <<EOT
module top(output wire [7:0] y);
assign y = 27;
endmodule
EOT
equiv_opt -assert bufnorm
design -load postopt
select -assert-count 1 t:$buf
select -assert-count 1 w:y %ci t:$buf %i