Merge branch 'YosysHQ:main' into main

tests/opt/bug4610.ys

@@ -0,0 +1,15 @@
+read_rtlil <<EOT
+autoidx 1
+module \top
+  wire output 1 \Y
+  cell $reduce_or $reduce_or$rtl.v:29$20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 0
+    parameter \Y_WIDTH 1
+    connect \A { }
+    connect \Y \Y
+  end
+end
+EOT
+
+equiv_opt -assert opt_demorgan

tests/opt/opt_reduce_andor.ys

@@ -0,0 +1,14 @@
+# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
+
+read_verilog <<EOT
+module reduce_const(output wire o, output wire a);
+    wire [3:0] zero = 4'b0000;
+    wire [3:0] ones = 4'b1111;
+    assign o = |zero;
+    assign a = &ones;
+endmodule
+EOT
+
+equiv_opt -assert opt_reduce
+design -load postopt
+select -assert-none r:A_WIDTH=0

tests/proc/bug4712.ys

@@ -0,0 +1,31 @@
+read_rtlil <<EOT
+autoidx 1
+module \top
+  wire input 1 \clk
+  wire input 2 \rst
+
+  wire input 3 \a_r
+  wire input 4 \a_n
+  wire input 5 \b_n
+
+  wire \a
+  wire \b
+
+  process $proc
+    sync high \rst
+      update \a \a_r
+      update \b \b
+    sync posedge \clk
+      update \a \a_n
+      update \b \b_n
+  end
+end
+EOT
+
+proc_dff
+proc_clean
+
+# Processes should have been converted to one aldff and one dff
+select -assert-none p:*
+select -assert-count 1 t:$aldff
+select -assert-count 1 t:$dff

tests/techmap/clockgate.lib

@@ -0,0 +1,107 @@
+library(test) {
+    /* Integrated clock gating cells */
+    cell (pos_small_tielo) {
+        area : 1;
+        clock_gating_integrated_cell : latch_posedge_precontrol;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+        pin (SE) {
+            clock_gate_test_pin : true;
+            direction : input;
+        }
+    }
+    cell (pos_big) {
+        area : 10;
+        clock_gating_integrated_cell : latch_posedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+    cell (pos_small) {
+        area : 1;
+        clock_gating_integrated_cell : latch_posedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+    cell (neg_big) {
+        area : 10;
+        clock_gating_integrated_cell : latch_negedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+    cell (neg_small_tielo) {
+        area : 1;
+        clock_gating_integrated_cell : latch_negedge_precontrol;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+        pin (SE) {
+            clock_gate_test_pin : true;
+            direction : input;
+        }
+    }
+    cell (neg_small) {
+        area : 1;
+        clock_gating_integrated_cell : latch_negedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+}

tests/techmap/clockgate.ys

@@ -61,7 +61,7 @@ clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
 # falling edge clock flops don't get matched on -pos
 select -module dffe_00 -assert-count 0 t:\\pdk_icg
 select -module dffe_01 -assert-count 0 t:\\pdk_icg
-# falling edge clock flops do get matched on -pos
+# rising edge clock flops do get matched on -pos
 select -module dffe_10 -assert-count 1 t:\\pdk_icg
 select -module dffe_11 -assert-count 1 t:\\pdk_icg
 # if necessary, EN is inverted, since the given ICG
@@ -79,10 +79,10 @@ select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
 design -load before
 clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
 
-# rising edge clock flops don't get matched on -neg
+# falling edge clock flops do get matched on -neg
 select -module dffe_00 -assert-count 1 t:\\pdk_icg
 select -module dffe_01 -assert-count 1 t:\\pdk_icg
-# rising edge clock flops do get matched on -neg
+# rising edge clock flops don't get matched on -neg
 select -module dffe_10 -assert-count 0 t:\\pdk_icg
 select -module dffe_11 -assert-count 0 t:\\pdk_icg
 # if necessary, EN is inverted, since the given ICG
@@ -193,4 +193,55 @@ select -assert-count 1 t:\\pdk_icg
 
 #------------------------------------------------------------------------------
 
-# TODO test -tie_lo
+design -load before
+clockgate -liberty clockgate.lib
+
+# rising edge ICGs
+select -module dffe_00 -assert-count 0 t:\\pos_small
+select -module dffe_01 -assert-count 0 t:\\pos_small
+
+select -module dffe_10 -assert-count 1 t:\\pos_small
+select -module dffe_11 -assert-count 1 t:\\pos_small
+
+# falling edge ICGs
+select -module dffe_00 -assert-count 1 t:\\neg_small
+select -module dffe_01 -assert-count 1 t:\\neg_small
+
+select -module dffe_10 -assert-count 0 t:\\neg_small
+select -module dffe_11 -assert-count 0 t:\\neg_small
+
+# and nothing else
+select -module dffe_00 -assert-count 0 t:\\pos_big
+select -module dffe_01 -assert-count 0 t:\\pos_big
+select -module dffe_10 -assert-count 0 t:\\pos_big
+select -module dffe_11 -assert-count 0 t:\\pos_big
+select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_00 -assert-count 0 t:\\neg_big
+select -module dffe_01 -assert-count 0 t:\\neg_big
+select -module dffe_10 -assert-count 0 t:\\neg_big
+select -module dffe_11 -assert-count 0 t:\\neg_big
+select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
+select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
+select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
+select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
+
+# if necessary, EN is inverted, since the given ICG
+# is assumed to have an active-high EN
+select -module dffe_10 -assert-count 1 t:\$_NOT_
+select -module dffe_11 -assert-count 0 t:\$_NOT_
+
+#------------------------------------------------------------------------------
+
+design -load before
+clockgate -liberty clockgate.lib -dont_use pos_small -dont_use neg_small
+
+# rising edge ICGs
+select -module dffe_10 -assert-count 1 t:\\pos_big
+select -module dffe_11 -assert-count 1 t:\\pos_big
+
+# falling edge ICGs
+select -module dffe_00 -assert-count 1 t:\\neg_big
+select -module dffe_01 -assert-count 1 t:\\neg_big