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Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width

opt_demorgan: skip zero width cells
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Emil J 2024-11-20 13:33:16 +01:00 committed by GitHub
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15
tests/opt/bug4610.ys Normal file
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@ -0,0 +1,15 @@
read_ilang <<EOT
autoidx 1
module \top
wire output 1 \Y
cell $reduce_or $reduce_or$rtl.v:29$20
parameter \A_SIGNED 0
parameter \A_WIDTH 0
parameter \Y_WIDTH 1
connect \A { }
connect \Y \Y
end
end
EOT
equiv_opt -assert opt_demorgan