Merge branch 'YosysHQ:main' into main

tests/liberty/.gitignore

@@ -1,3 +1,3 @@
 *.log
-*.filtered
+/*.filtered
 *.verilogsim

tests/liberty/foundry_data/.gitignore

@@ -0,0 +1,2 @@
+*.lib
+*.lib.filtered

tests/liberty/foundry_data/rules.txt

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+-wire_load
+-wire_load_selection
+-default_wire_load
+-default_wire_load_area
+-default_wire_load_capacitance
+-default_wire_load_mode
+-default_wire_load_resistance
+-default_cell_leakage_power
+-default_wire_load_selection
+-default_leakage_power_density
+-lu_table_template
+-power_lut_template
+-leakage_power
+-cell_leakage_power
+-leakage_power
+-internal_power

tests/liberty/options_test.ys

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+# Test memory macro gets ignored due to -ignore_buses
+read_verilog -noblackbox <<EOF
+module RM_IHPSG13_1P_64x64_c2_bm_bist();
+endmodule
+EOF
+read_liberty -lib -ignore_buses foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
+
+# Test memory macro doesn't get ignored without -ignore_buses
+# and check the area and capacitance attributes are populated
+design -reset
+read_liberty -lib foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
+select -assert-mod-count 1 =RM_IHPSG13_1P_64x64_c2_bm_bist =A:area=50489.1328 %i
+select -assert-any =*/i:A_BIST_EN =*/a:capacitance=0.00401111 %i
+
+# Test import of unit delay arcs
+design -reset
+read_liberty -wb -unit_delay -ignore_miss_func foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
+
+# A->Y arc on nand2_1 exists
+select -assert-any =sg13g2_nand2_1/i:A %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Y %co1:+$specify2[DST] %i
+
+# D->Q arc on sdfbbp_1 doesn't
+select -assert-none =sg13g2_sdfbbp_1/i:D %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Q %co1:+$specify2[DST] %i

tests/liberty/unit_delay.ys

@@ -1,3 +0,0 @@
-# Nothing gets imported: the file lacks timing data
-read_liberty -wb -unit_delay normal.lib
-select -assert-none =*/t:$specify*

tests/memories/nordports.ys

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+# check memory_collect doesn't produce invalid RTLIL on a memory w/o read ports
+read_rtlil <<EOF
+autoidx 1
+attribute \top 1
+module \top
+  memory width 4 size 3 \foo
+end
+EOF
+memory_collect