mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
Merge branch 'YosysHQ:main' into main
This commit is contained in:
commit
6e88c689f2
20 changed files with 196 additions and 24 deletions
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@ -20,6 +20,13 @@ generate_ys_test() {
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generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args_ $ys_file"
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}
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# $ generate_tcl_test tcl_file [yosys_args]
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generate_tcl_test() {
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tcl_file=$1
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yosys_args_=${2:-}
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generate_target "$tcl_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${tcl_file%.*}.log $yosys_args_ $tcl_file"
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}
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# $ generate_bash_test bash_file
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generate_bash_test() {
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bash_file=$1
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@ -29,6 +36,7 @@ generate_bash_test() {
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# $ generate_tests [-y|--yosys-scripts] [-s|--prove-sv] [-b|--bash] [-a|--yosys-args yosys_args]
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generate_tests() {
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do_ys=false
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do_tcl=false
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do_sv=false
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do_sh=false
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yosys_args=""
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@ -40,6 +48,10 @@ generate_tests() {
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do_ys=true
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shift
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;;
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-t|--tcl-scripts)
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do_tcl=true
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shift
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;;
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-s|--prove-sv)
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do_sv=true
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shift
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@ -59,7 +71,7 @@ generate_tests() {
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esac
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done
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if [[ ! ( $do_ys = true || $do_sv = true || $do_sh = true ) ]]; then
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if [[ ! ( $do_ys = true || $do_tcl = true || $do_sv = true || $do_sh = true ) ]]; then
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echo >&2 "Error: No file types selected"
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exit 1
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fi
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@ -72,6 +84,11 @@ generate_tests() {
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generate_ys_test "$x" "$yosys_args"
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done
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fi;
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if [[ $do_tcl = true ]]; then
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for x in *.tcl; do
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generate_tcl_test "$x" "$yosys_args"
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done
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fi;
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if [[ $do_sv = true ]]; then
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for x in *.sv; do
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if [ ! -f "${x%.sv}.ys" ]; then
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15
tests/techmap/han-carlson.tcl
Normal file
15
tests/techmap/han-carlson.tcl
Normal file
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@ -0,0 +1,15 @@
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yosys -import
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read_verilog +/choices/han-carlson.v
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read_verilog -icells lcu_refined.v
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design -save init
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for {set i 1} {$i <= 16} {incr i} {
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design -load init
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chparam -set WIDTH $i
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yosys proc
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opt_clean
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equiv_make lcu _80_lcu_han_carlson equiv
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equiv_simple equiv
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equiv_status -assert equiv
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}
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15
tests/techmap/kogge-stone.tcl
Normal file
15
tests/techmap/kogge-stone.tcl
Normal file
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@ -0,0 +1,15 @@
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yosys -import
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read_verilog +/choices/kogge-stone.v
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read_verilog -icells lcu_refined.v
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design -save init
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for {set i 1} {$i <= 16} {incr i} {
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design -load init
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chparam -set WIDTH $i
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yosys proc
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opt_clean
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equiv_make lcu _80_lcu_kogge_stone equiv
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equiv_simple equiv
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equiv_status -assert equiv
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}
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@ -1 +0,0 @@
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test_cell -s 1711533949 -n 10 -map +/techmap.v -map +/choices/kogge-stone.v $lcu
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13
tests/techmap/lcu_refined.v
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13
tests/techmap/lcu_refined.v
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@ -0,0 +1,13 @@
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module lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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input [WIDTH-1:0] P, G;
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input CI;
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output [WIDTH-1:0] CO;
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reg [WIDTH-1:0] p, g;
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\$lcu #(.WIDTH(WIDTH)) impl (.P(P), .G(G), .CI(CI), .CO(CO));
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endmodule
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@ -1,4 +1,4 @@
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#!/usr/bin/env bash
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set -eu
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source ../gen-tests-makefile.sh
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run_tests --yosys-scripts --bash --yosys-args "-e 'select out of bounds'"
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run_tests --yosys-scripts --tcl-scripts --bash --yosys-args "-e 'select out of bounds'"
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24
tests/verific/blackbox.ys
Normal file
24
tests/verific/blackbox.ys
Normal file
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@ -0,0 +1,24 @@
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verific -sv -lib <<EOF
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module TEST_CELL(input clk, input a, input b, output reg c);
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parameter PATH = "DEFAULT";
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always @(posedge clk) begin
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if (PATH=="DEFAULT")
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c <= a;
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else
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c <= b;
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end
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endmodule
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EOF
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verific -sv <<EOF
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module top(input clk, input a, input b, output c, output d);
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TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
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TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
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endmodule
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EOF
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verific -import top
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hierarchy -top top
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stat
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select -assert-count 2 t:TEST_CELL
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