Add more Liberty tests and fix parentheses in functions

passes/techmap/libparse.cc

@@ -236,9 +236,12 @@ LibertyAst *LibertyParser::parse()
 			if (tok == 'v') {
     				tok = lexer(str);
 			}
-			while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') {
+			while (tok == '(' || tok == ')' || tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { // SILIMATE: added parentheses
 				ast->value += tok;
-				tok = lexer(str);
+				if (tok == ')') { // SILIMATE: semicolon may follow close parenthesis
+					tok = lexer(str);
+					if (tok == ';') break;
+				} else tok = lexer(str);
 				if (tok != 'v')
 					error();
 				ast->value += str;

tests/liberty/parenfunc.lib

@@ -0,0 +1,100 @@
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  input_threshold_pct_rise : 50;
+  input_threshold_pct_fall : 50;
+  output_threshold_pct_rise : 50;
+  output_threshold_pct_fall : 50;
+  slew_lower_threshold_pct_rise : 30;
+  slew_lower_threshold_pct_fall : 30;
+  slew_upper_threshold_pct_rise : 70;
+  slew_upper_threshold_pct_fall : 70;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+  /* Latch */
+  cell(latch) {
+    area : 5;
+    latch ("IQ","IQN") {
+      enable : (G);
+      data_in : "D";
+    }
+
+    pin(D) {
+      direction : input;
+    }
+    pin(G) {
+      direction : input;
+    }
+ 
+    pin(Q) {
+      direction : output;
+      function : "IQ";
+      internal_node : "Q";
+      
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "G";
+      }
+      
+      timing() {
+        timing_sense : positive_unate;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "D";
+      }
+    }
+    
+    pin(QN) {
+      direction : output;
+      function : "IQN";
+      internal_node : "QN";
+      
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "G";
+      }
+      
+      timing() {
+        timing_sense : negative_unate;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "D";
+      }
+    }
+  }
+}

tests/liberty/parenfunc.lib.filtered.ok

@@ -0,0 +1,23 @@
+library(supergate) {
+  cell(latch) {
+    area : 5 ;
+    latch(IQ, IQN) {
+      enable : (G) ;
+      data_in : D ;
+    }
+    pin(D) {
+      direction : input ;
+    }
+    pin(G) {
+      direction : input ;
+    }
+    pin(Q) {
+      direction : output ;
+      function : IQ ;
+    }
+    pin(QN) {
+      direction : output ;
+      function : IQN ;
+    }
+  }
+}

tests/liberty/parenfunc.lib.verilogsim.ok

@@ -0,0 +1,15 @@
+module latch (D, G, Q, QN);
+  reg IQ, IQN;
+  input D;
+  input G;
+  output Q;
+  assign Q = IQ; // IQ
+  output QN;
+  assign QN = IQN; // IQN
+  always @* begin
+    if ((G)) begin
+      IQ <= D;
+      IQN <= ~(D);
+    end
+  end
+endmodule

tests/liberty/strangecolons.lib

@@ -0,0 +1,55 @@
+library (strange_colons) {
+  delay_model : "table_lookup";
+  simulation : false;
+  capacitive_load_unit (1,pF);
+  leakage_power_unit : "1pW";
+  current_unit : "1A";
+  pulling_resistance_unit : "1kohm";
+  time_unit : "1ns";
+  voltage_unit : "1v";
+  library_features : "report_delay_calculation";
+  input_threshold_pct_rise : 50;
+  input_threshold_pct_fall : 50;
+  output_threshold_pct_rise : 50;
+  output_threshold_pct_fall : 50;
+  slew_lower_threshold_pct_rise : 30;
+  slew_lower_threshold_pct_fall : 30;
+  slew_upper_threshold_pct_rise : 70;
+  slew_upper_threshold_pct_fall : 70;
+  slew_derate_from_library : 1.0;
+  nom_process : 1.0;
+  nom_temperature : 85.0;
+  nom_voltage : 0.75;
+
+  cell(strange_colons) { 
+    sensitization_master : sensitization_3pins ; 
+    area : 0.1 ; 
+    dont_touch : true ; 
+    dont_use : true ; 
+
+    pin(A) { 
+      capacitance : 0.0001 ; 
+      direction : input ; 
+      driver_waveform_rise : "driver_waveform_default_rise" ; 
+      driver_waveform_fall : "driver_waveform_default_fall" ; 
+      fall_capacitance : 0.0001 ; 
+      input_voltage : default ; 
+      max_transition : 0.1 ; 
+      related_ground_pin : VSS ; 
+      related_power_pin : VDD ; 
+      rise_capacitance : 0.0001 ; 
+      active_input_ccb(strange_colons:ck);
+      active_input_ccb(strange_colons:d, \
+                       strange_colons:d);
+      propagating_ccb(strange_colons:a, strange_colons:y);
+
+      input_ccb(strange_colons:a) { 
+        is_needed : true ; 
+        is_inverting : true ; 
+        miller_cap_fall : 0.0001 ; 
+        miller_cap_rise : 1e-05 ; 
+        stage_type : both ; 
+      }
+    }
+  }
+}

tests/liberty/strangecolons.lib.filtered.ok

@@ -0,0 +1,10 @@
+library(strange_colons) {
+  cell(strange_colons) {
+    area : 0.1 ;
+    dont_touch : true ;
+    dont_use : true ;
+    pin(A) {
+      direction : input ;
+    }
+  }
+}