3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-09 11:52:23 +00:00
yosys/tests
2024-11-20 15:04:00 +01:00
..
aiger read_aiger: Fix incorrect read of binary Aiger without outputs 2024-04-29 14:06:58 +01:00
arch Remove references to ilang 2024-11-05 12:36:31 +13:00
asicworld
bind
blif
bram
cxxrtl cxxrtl: test stream operator 2024-10-01 13:25:07 +02:00
errors
fmt
fsm
functional functional tests: run from make tests but not smtlib/rkt tests 2024-09-04 10:30:08 +01:00
hana
liberty read_liberty: s/busses/buses/ 2024-11-12 13:33:41 +01:00
lut
memfile
memlib
memories rtlil: Adjust internal check for $mem_v2 cells 2024-11-08 15:18:43 +01:00
opt tests: replace read_ilang with read_rtlil 2024-11-20 14:54:23 +01:00
opt_share
proc Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs 2024-11-20 13:26:32 +01:00
realmath
rpc Remove references to ilang 2024-11-05 12:36:31 +13:00
sat Remove references to ilang 2024-11-05 12:36:31 +13:00
select Merge pull request #4700 from povik/select-list-mod 2024-11-04 15:38:42 +00:00
share
sim Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing 2024-11-06 16:29:07 +01:00
simple
simple_abc9
smv Remove references to ilang 2024-11-05 12:36:31 +13:00
sva
svinterfaces
svtypes
techmap clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
tools
unit rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
various Merge pull request #4525 from georgerennie/peepopt_clock_gate 2024-11-11 14:49:09 +01:00
verific Add left and right bound properties to wire. Add test. Fix printing 2024-09-10 12:52:42 +02:00
verilog Remove references to ilang 2024-11-05 12:36:31 +13:00
vloghtb
xprop
gen-tests-makefile.sh