Merge branch 'YosysHQ:main' into main

tests/sim/assume_x_first_step.ys

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+read_verilog simple_assign.v
+sim -r simple_assign.vcd -scope simple_assign

tests/sim/simple_assign.v

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+module simple_assign (
+    input wire in,
+    output wire out
+);
+
+    assign out = in;
+
+endmodule

tests/sim/simple_assign.vcd

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+$version Yosys $end
+$scope module simple_assign $end
+$var wire 1 n2 in $end
+$var wire 1 n1 out $end
+$upscope $end
+$enddefinitions $end
+#0
+#5
+b1 n1
+b1 n2
+#10
+b0 n1
+b0 n2

tests/sim/var_reference_with_whitespace.vcd

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+$date
+  Fri Sep 27 11:58:46 2024
+$end
+$version
+  GHDL v0
+$end
+$timescale
+  1 fs
+$end
+$scope module standard $end
+$upscope $end
+$scope module std_logic_1164 $end
+$upscope $end
+$scope module tb $end
+$var reg 4 ! a [3:0] $end
+$var reg 4 " b [3:0] $end
+$scope module uut $end
+$var reg 4 # a [3:0] $end
+$var reg 4 $ b [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+b0001 !
+b0001 "
+b0001 #
+b0001 $
+#10000000

tests/sim/var_reference_without_whitespace.vcd

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+$date
+  Fri Sep 27 11:58:46 2024
+$end
+$version
+  GHDL v0
+$end
+$timescale
+  1 fs
+$end
+$scope module standard $end
+$upscope $end
+$scope module std_logic_1164 $end
+$upscope $end
+$scope module tb $end
+$var reg 4 ! a[3:0] $end
+$var reg 4 " b[3:0] $end
+$scope module uut $end
+$var reg 4 # a[3:0] $end
+$var reg 4 $ b[3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+b0001 !
+b0001 "
+b0001 #
+b0001 $
+#10000000

tests/sim/vcd_var_reference_whitespace.ys

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+read_rtlil vector_assign.il
+sim -r var_reference_without_whitespace.vcd -scope tb.uut
+sim -r var_reference_with_whitespace.vcd -scope tb.uut

tests/sim/vector_assign.il

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+# Generated by Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)
+autoidx 2
+attribute \architecture "Behavioral"
+attribute \library "work"
+attribute \hdlname "vector_assign"
+attribute \src "tests/verific/vector_assign.vhd:4.8-4.21"
+module \vector_assign
+  attribute \src "tests/verific/vector_assign.vhd:6.9-6.10"
+  wire width 4 input 2 \a
+  attribute \src "tests/verific/vector_assign.vhd:7.9-7.10"
+  wire width 4 output 1 \b
+  attribute \src "tests/verific/vector_assign.vhd:13.5-13.6"
+  cell $pos $verific$buf_3$tests/verific/vector_assign.vhd:13$1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \a
+    connect \Y \b
+  end
+end