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15823 commits 122 branches 59 tags 72 MiB
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2167 commits

Author SHA1 Message Date
Eddie Hung
7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
Eddie Hung
ebb11bcea4 iopadmap: move \init attributes from outpad output to its input 2020-02-13 12:05:14 -08:00
N. Engelhardt
c2467fdd55 make rpc frontend unix socket test less fragile 2020-02-13 20:52:22 +01:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Eddie Hung
d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master 
$readmem[hb] file inclusion is now relative to the Verilog file
 2020-02-10 08:31:01 -08:00
Marcin Kościelnicki
89adef352f xilinx: Add support for LUT RAM on LUT4-based devices. 
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
 2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d xilinx: Initial support for LUT4 devices. 
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
 2020-02-07 09:03:22 +01:00
whitequark
081d9318bc ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
 2020-02-06 16:52:51 +00:00
whitequark
3f4460a186 ice40: match memory inference attribute values case insensitive. 
LSE/Synplify use case insensitive matching.
 2020-02-06 14:58:20 +00:00
whitequark
fc28bf55aa ice40: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify appear to interpret attribute values insensitive
    to case. There is currently no way to do this in Yosys (attrmap
    can only change case of attribute names).
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
 2020-02-06 14:58:20 +00:00
whitequark
29d130dee9 ice40: remove impossible test. 
iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
 2020-02-06 14:58:20 +00:00
Rodrigo Alejandro Melo
9da5936c05 Added 'set -e' into tests/memfile/run-test.sh 
Also added two checks for situations where the execution must fail.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-06 10:45:40 -03:00
Eddie Hung
4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 
opt_merge: discard \init of '$' cells with 'Q' port when merging
 2020-02-05 14:56:26 -08:00
Eddie Hung
6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux 
techmap LSB-first for compatible $shift/$shiftx cells
 2020-02-05 14:55:57 -08:00
Eddie Hung
0b308c6835 abc9_ops: -reintegrate to use derived_type for box_ports 2020-02-05 14:46:48 -08:00
Eddie Hung
b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631 
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
 2020-02-05 19:31:18 +01:00
Stefan Biereigel
90c78f1f85 add testcase for #1614 2020-02-03 21:29:54 +01:00
Rodrigo A. Melo
665a967d87
Merge branch 'master' into master 2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo
313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
David Shah
ebe1d7d5ab sv: More tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
a210675d71 sv: Add tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo
8217f579b7 Removed 'synth' into tests/memfile/run-test.sh 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo
9b49f1bc46 Added content1.dat into tests/memfile 
Modified run-test.sh to use it.

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-02 12:18:34 -03:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf 
ast: Add support for $sformatf system function
 2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo
eaaba6e091 Added tests/memfile to 'make test' with an extra testcase 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo
43396fae2c Added a test for the Memory Content File inclusion using $readmemb 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:41:10 -03:00
Eddie Hung
136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00
Miodrag Milanović
71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix 
Fix for non-deterministic test
 2020-01-29 11:18:06 +01:00
Eddie Hung
d004953772 Add "help -all" and "help -celltypes" sanity test 2020-01-28 18:11:34 -08:00
Eddie Hung
a855f23f22 Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init 2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Miodrag Milanovic
94191a93dd Updated test to use assert-max 2020-01-28 18:26:10 +01:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning 
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
 2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
Eddie Hung
cfb0366a18 Import tests from #1628 2020-01-27 13:56:16 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung
af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings 
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
 2020-01-27 09:54:04 -08:00
Eddie Hung
b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung
2d795fb8c0 simple_abc9 tests to discard whitebox before write for sim 2020-01-23 22:07:43 -08:00
Eddie Hung
dca1c806ec simple_abc9 tests to discard whitebox before write for sim 2020-01-23 19:55:11 -08:00
Eddie Hung
e471b330ac abc_box_id -> abc9_box_id in test 2020-01-23 19:12:19 -08:00
Eddie Hung
11e50c0e9e Test for (* keep *)-ed abc9_box_id 2020-01-23 18:56:25 -08:00
Eddie Hung
48aec34e0d abc_box_id -> abc9_box_id in test 2020-01-23 18:53:14 -08:00
Eddie Hung
5aaa19f1ab Update tests with reduced area 2020-01-21 16:50:04 -08:00
Eddie Hung
3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung
8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00