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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

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Eddie Hung 2020-01-21 16:27:40 -08:00
commit 3d9737c1bd
16 changed files with 365 additions and 156 deletions
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tests/arch/ice40/bug1644.il.gz Normal file
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tests/arch/ice40/bug1644.ys Normal file
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read_ilang bug1644.il.gz
synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram

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tests/arch/ice40/ice40_dsp.ys Normal file
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read_verilog <<EOT
module top(input [15:0] a, b, output [31:0] o1, o2, o5);
SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1));
assign o2 = a * 16'd0;
wire [31:0] o3, o4;
SB_MAC16 m2 (.A(a), .B(b), .O(o3));
assign o4 = a * b;
SB_MAC16 m3 (.A(a), .B(b), .O(o5));
endmodule
EOT
ice40_dsp

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tests/various/bug1462.ys → tests/arch/xilinx/bug1462.ys
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tests/arch/xilinx/xilinx_dsp.ys Normal file
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read_verilog <<EOT
module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5);
DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1));
assign o2 = a * 16'd0;
wire [42:0] o3, o4;
DSP48E1 m2 (.A(a), .B(b), .P(o3));
assign o4 = a * b;
DSP48E1 m3 (.A(a), .B(b), .P(o5));
endmodule
EOT
xilinx_dsp