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Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux

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This commit is contained in:
Eddie Hung 2020-02-05 10:47:31 -08:00
commit b6a1f627b5
77 changed files with 4480 additions and 1957 deletions
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32
tests/arch/ecp5/opt_lut_ins.ys Normal file
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@ -0,0 +1,32 @@
read_ilang << EOF
module \top
wire input 1 \A
wire input 2 \B
wire input 3 \C
wire input 4 \D
wire output 5 \Z
cell \LUT4 $0
parameter \INIT 16'1111110011000000
connect \A \A
connect \B \B
connect \C \C
connect \D \D
connect \Z \Z
end
end
EOF
read_verilog -lib +/ecp5/cells_sim.v
equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech ecp5
design -load postopt
select -assert-count 1 top/t:LUT4
select -assert-count 0 top/w:A %co top/t:LUT4 %i
select -assert-count 1 top/w:B %co top/t:LUT4 %i

2
tests/arch/efinix/mux.ys
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@ -36,6 +36,6 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 11 t:EFX_LUT4
select -assert-max 12 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D

8
tests/arch/gowin/mux.ys
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@ -18,13 +18,13 @@ proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 4 t:LUT4
select -assert-count 4 t:LUT*
select -assert-count 2 t:MUX2_LUT5
select -assert-count 1 t:MUX2_LUT6
select -assert-count 6 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux8
@ -35,7 +35,7 @@ cd mux8 # Constrain all select calls below inside the top module
select -assert-count 11 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux16
@ -46,4 +46,4 @@ cd mux16 # Constrain all select calls below inside the top module
select -assert-count 20 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
select -assert-none t:GND t:VCC t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D

72
tests/arch/ice40/bug1597.ys Normal file
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@ -0,0 +1,72 @@
read_verilog <<EOT
module top (
input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5,
PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25,
output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18,
PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24,
);
assign USBPU = 0;
wire[5:0] parOut;
wire[5:0] chrg;
assign PIN_14 = parOut[0];
assign PIN_15 = parOut[1];
assign PIN_16 = parOut[2];
assign PIN_17 = parOut[3];
assign PIN_18 = parOut[4];
assign PIN_19 = parOut[5];
assign chrg[0] = PIN_3;
assign chrg[1] = PIN_4;
assign chrg[2] = PIN_5;
assign chrg[3] = PIN_6;
assign chrg[4] = PIN_7;
assign chrg[5] = PIN_8;
SSCounter6o sc6(PIN_1, CLK, PIN_2, PIN_9, chrg, parOut);
endmodule
module SSCounter6 (input wire rst, clk, adv, jmp, input wire [5:0] in, output reg[5:0] out);
always @(posedge clk, posedge rst)
if (rst) out <= 0;
else if (adv || jmp) out <= jmp ? in : out + 1;
endmodule
// Optimized 6 bit counter, it should takes 7 cells.
/* b[5:1] /* b[0]
1010101010101010 in 1010101010101010 in
1100110011001100 jmp 1100110011001100 jmp
1111000011110000 loop 1111000011110000 loop
1111111100000000 carry 1111111100000000 -
---------------------- ----------------------
1000101110111000 out 1000101110001011 out
8 B B 8 8 B 8 B
*/
module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output wire[5:0] out);
wire[4:0] co;
wire[5:0] lo;
wire ien;
SB_LUT4 #(.LUT_INIT(16'hFFF0)) lien (ien, 0, 0, adv, jmp);
SB_CARRY c0 (co[0], jmp, out[0], 1),
c1 (co[1], jmp, out[1], co[0]),
c2 (co[2], jmp, out[2], co[1]),
c3 (co[3], jmp, out[3], co[2]),
c4 (co[4], jmp, out[4], co[3]);
SB_DFFER d0 (out[0], clk, ien, rst, lo[0]),
d1 (out[1], clk, ien, rst, lo[1]),
d2 (out[2], clk, ien, rst, lo[2]),
d3 (out[3], clk, ien, rst, lo[3]),
d4 (out[4], clk, ien, rst, lo[4]),
d5 (out[5], clk, ien, rst, lo[5]);
SB_LUT4 #(.LUT_INIT(16'h8B8B)) l0 (lo[0], in[0], jmp, out[0], 0);
SB_LUT4 #(.LUT_INIT(16'h8BB8)) l1 (lo[1], in[1], jmp, out[1], co[0]);
SB_LUT4 #(.LUT_INIT(16'h8BB8)) l2 (lo[2], in[2], jmp, out[2], co[1]);
SB_LUT4 #(.LUT_INIT(16'h8BB8)) l3 (lo[3], in[3], jmp, out[3], co[2]);
SB_LUT4 #(.LUT_INIT(16'h8BB8)) l4 (lo[4], in[4], jmp, out[4], co[3]);
SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
endmodule
EOT
hierarchy -top top
flatten
equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40

57
tests/arch/ice40/ice40_opt.ys
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@ -1,23 +1,3 @@
read_verilog -icells -formal <<EOT
module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
\$lut #(
.WIDTH(4),
.LUT(LUT)
) lut (
.A({I0,A,B,I3}),
.Y(O)
);
endmodule
EOT
design -stash unmap
read_verilog -icells -formal <<EOT
module top(input CI, I0, output [1:0] CO, output O);
wire A = 1'b0, B = 1'b0;
@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O);
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
.LUT(~16'b 0110_1001_1001_0110)
.LUT(~16'b 0110_1001_1001_0110),
.I3_IS_CI(1'b1)
) u0 (
.A(A),
.B(B),
.CI(CI),
.I0(I0),
.I3(CI),
.I3(1'bx),
.CO(CO[0]),
.O(O)
);
@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule
EOT
equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:$lut
@ -105,3 +86,33 @@ select -assert-count 1 t:SB_LUT4
select -assert-count 1 t:SB_CARRY
select -assert-count 1 t:SB_CARRY a:keep %i
select -assert-count 1 t:SB_CARRY c:carry %i
design -reset
read_verilog -icells <<EOT
module top(input I3, I2, I1, I0, output O, O2);
SB_LUT4 #(
.LUT_INIT(8'b 1001_0110)
) u0 (
.I0(I0),
.I1(I1),
.I2(I2),
.I3(),
.O(O)
);
wire CO;
\$__ICE40_CARRY_WRAPPER #(
.LUT(~8'b 1001_0110),
.I3_IS_CI(1'b0)
) u1 (
.A(1'b0),
.B(1'b0),
.CI(1'b0),
.I0(),
.I3(),
.CO(CO),
.O(O2)
);
endmodule
EOT
ice40_opt

25
tests/arch/xilinx/opt_lut_ins.ys Normal file
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@ -0,0 +1,25 @@
read_ilang << EOF
module \top
wire width 4 input 1 \A
wire output 2 \O
cell \LUT4 $0
parameter \INIT 16'1111110011000000
connect \I0 \A [0]
connect \I1 \A [1]
connect \I2 \A [2]
connect \I3 \A [3]
connect \O \O
end
end
EOF
equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
design -load postopt
select -assert-count 1 t:LUT3

5
tests/arch/xilinx/tribuf.sh Normal file
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@ -0,0 +1,5 @@
! ../../../yosys ../common/tribuf.v -qp "synth_xilinx"
../../../yosys ../common/tribuf.v -qp "synth_xilinx -iopad; \
select -assert-count 2 t:IBUF; \
select -assert-count 1 t:INV; \
select -assert-count 1 t:OBUFT"

23
tests/opt/opt_lut_ins.ys Normal file
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@ -0,0 +1,23 @@
read_ilang << EOF
module \top
wire width 4 input 1 \A
wire output 2 \Y
cell $lut \lut
parameter \LUT 16'1111110011000000
parameter \WIDTH 4
connect \A \A
connect \Y \Y
end
end
EOF
equiv_opt -assert opt_lut_ins
design -load postopt
select -assert-count 1 t:$lut r:WIDTH=3 %i

66
tests/sat/clk2fflogic.ys Normal file
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@ -0,0 +1,66 @@
read_verilog -icells <<EOT
module top(input clk, d, s, r, output reg [17:0] q);
always @(posedge clk or posedge s) if ( s) q[ 0] <= 1'b1; else q[ 0] <= d;
always @(posedge clk or negedge s) if (!s) q[ 1] <= 1'b1; else q[ 1] <= d;
always @(posedge clk or posedge r) if ( r) q[ 2] <= 1'b0; else q[ 2] <= d;
always @(posedge clk or negedge r) if (!r) q[ 3] <= 1'b0; else q[ 3] <= d;
always @(negedge clk or posedge s) if ( s) q[ 4] <= 1'b1; else q[ 4] <= d;
always @(negedge clk or negedge s) if (!s) q[ 5] <= 1'b1; else q[ 5] <= d;
always @(negedge clk or posedge r) if ( r) q[ 6] <= 1'b0; else q[ 6] <= d;
always @(negedge clk or negedge r) if (!r) q[ 7] <= 1'b0; else q[ 7] <= d;
// Seems like proc_dlatch always sets {SET,CLR}_POLARITY to true
always @(posedge clk or posedge s or posedge r) if ( r) q[ 8] <= 1'b0; else if ( s) q[ 8] <= 1'b1; else q[ 8] <= d;
//always @(posedge clk or posedge s or negedge r) if (!r) q[ 9] <= 1'b0; else if ( s) q[ 9] <= 1'b1; else q[ 9] <= d;
//always @(posedge clk or negedge s or posedge r) if ( r) q[10] <= 1'b0; else if (!s) q[10] <= 1'b1; else q[10] <= d;
//always @(posedge clk or negedge s or negedge r) if (!r) q[11] <= 1'b0; else if (!s) q[11] <= 1'b1; else q[11] <= d;
$dffsr #(.CLK_POLARITY(1'h1), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h1), .WIDTH(32'd1)) ppn (.CLK(clk), .CLR(r), .D(d), .Q(q[ 9]), .SET(s));
$dffsr #(.CLK_POLARITY(1'h1), .CLR_POLARITY(1'h1), .SET_POLARITY(1'h0), .WIDTH(32'd1)) pnp (.CLK(clk), .CLR(r), .D(d), .Q(q[10]), .SET(s));
$dffsr #(.CLK_POLARITY(1'h1), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h0), .WIDTH(32'd1)) pnn (.CLK(clk), .CLR(r), .D(d), .Q(q[11]), .SET(s));
always @(negedge clk or posedge s or posedge r) if ( r) q[12] <= 1'b0; else if ( s) q[12] <= 1'b1; else q[12] <= d;
//always @(negedge clk or posedge s or negedge r) if (!r) q[13] <= 1'b0; else if ( s) q[13] <= 1'b1; else q[13] <= d;
//always @(negedge clk or negedge s or posedge r) if ( r) q[14] <= 1'b0; else if (!s) q[14] <= 1'b1; else q[14] <= d;
//always @(negedge clk or negedge s or negedge r) if (!r) q[15] <= 1'b0; else if (!s) q[15] <= 1'b1; else q[15] <= d;
$dffsr #(.CLK_POLARITY(1'h0), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h1), .WIDTH(32'd1)) npn (.CLK(clk), .CLR(r), .D(d), .Q(q[13]), .SET(s));
$dffsr #(.CLK_POLARITY(1'h0), .CLR_POLARITY(1'h1), .SET_POLARITY(1'h0), .WIDTH(32'd1)) nnp (.CLK(clk), .CLR(r), .D(d), .Q(q[14]), .SET(s));
$dffsr #(.CLK_POLARITY(1'h0), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h0), .WIDTH(32'd1)) nnn (.CLK(clk), .CLR(r), .D(d), .Q(q[15]), .SET(s));
always @(posedge clk) q[16] <= d;
always @(negedge clk) q[17] <= d;
endmodule
EOT
proc
select -assert-count 8 t:$adff
select -assert-count 8 t:$dffsr
select -assert-count 2 t:$dff
design -save gold
simplemap
select -assert-count 1 t:$_DFF_NN0_
select -assert-count 1 t:$_DFF_NN1_
select -assert-count 1 t:$_DFF_NP0_
select -assert-count 1 t:$_DFF_NP1_
select -assert-count 1 t:$_DFF_PN0_
select -assert-count 1 t:$_DFF_PN1_
select -assert-count 1 t:$_DFF_PP0_
select -assert-count 1 t:$_DFF_PP1_
stat
select -assert-count 1 t:$_DFFSR_NNN_
select -assert-count 1 t:$_DFFSR_NNP_
select -assert-count 1 t:$_DFFSR_NPN_
select -assert-count 1 t:$_DFFSR_NPP_
select -assert-count 1 t:$_DFFSR_PNN_
select -assert-count 1 t:$_DFFSR_PNP_
select -assert-count 1 t:$_DFFSR_PPN_
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:$_DFF_N_
select -assert-count 1 t:$_DFF_P_
design -stash gate
design -import gold -as gold
design -import gate -as gate
clk2fflogic
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -set-init-undef -seq 10 miter

11
tests/sat/initval.ys
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@ -2,3 +2,14 @@ read_verilog -sv initval.v
proc;;
sat -seq 10 -prove-asserts
design -reset
read_verilog -icells <<EOT
module top(input clk, i, output [1:0] o);
(* init = 2'bx0 *)
wire [1:0] o;
assign o[1] = o[0];
$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0]));
endmodule
EOT
sat -seq 1

18
tests/simple_abc9/abc9.v
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@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode
input rst;
endmodule
(* abc_box_id=1 *)
(* abc9_box_id=1, whitebox *)
module MUXF8(input I0, I1, S, output O);
endmodule
@ -291,3 +291,19 @@ module abc9_test035(input clk, d, output reg [1:0] q);
always @(posedge clk) q[0] <= d;
always @(negedge clk) q[1] <= q[0];
endmodule
module abc9_test036(input A, B, S, output [1:0] O);
(* keep *)
MUXF8 m (
.I0(I0),
.I1(I1),
.O(O[0]),
.S(S)
);
MUXF8 m2 (
.I0(I0),
.I1(I1),
.O(O[1]),
.S(S)
);
endmodule

3
tests/simple_abc9/run-test.sh
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@ -28,4 +28,5 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p
abc9 -lut 4 -box ../abc.box; \
clean; \
check -assert; \
select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
setattr -mod -unset whitebox'"

29
tests/techmap/abc9.ys
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@ -39,6 +39,35 @@ design -load gold
scratchpad -copy abc9.script.flow3 abc9.script
abc9 -lut 4
design -reset
read_verilog <<EOT
module top(input a, b, output o);
(* keep *) wire w = a & b;
assign o = ~w;
endmodule
EOT
simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 2 t:$lut
design -reset
read_verilog -icells <<EOT
module top(input a, b, output o);
wire w;
(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
assign o = ~w;
endmodule
EOT
simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 1 t:$lut
select -assert-count 1 t:$_AND_
design -reset
read_verilog -icells <<EOT

15
tests/various/abc9.ys
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@ -14,6 +14,7 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top abc9_test028
proc
@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
select -assert-count 1 t:unknown
select -assert-none t:$lut t:unknown %% t: %D
design -load read
hierarchy -top abc9_test032
proc
@ -38,3 +40,16 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -seq 10 -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module abc9_test036(input clk, d, output q);
(* keep *) reg w;
$__ABC9_FF_ ff(.D(d), .Q(w));
wire \ff.clock = clk;
wire \ff.init = 1'b0;
assign q = w;
endmodule
EOT
abc9 -lut 4 -dff

2
tests/various/help.ys Normal file
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@ -0,0 +1,2 @@
help -all
help -celltypes

12
tests/various/sformatf.ys Normal file
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@ -0,0 +1,12 @@
read_verilog <<EOT
module top;
localparam a = $sformatf("0x%x", 8'h5A);
localparam b = $sformatf("%d", 4'b011);
generate
if (a != "0x5a") $error("a incorrect!");
if (b != "3") $error("b incorrect!");
endgenerate
endmodule
EOT

124
tests/various/sv_implicit_ports.sh Executable file
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@ -0,0 +1,124 @@
#!/bin/bash
trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
# Simple case
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
wire [7:0] b = 8'd42;
add add_i(.*);
endmodule
EOT
# Generate block
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
generate
if (1) begin:ablock
wire [7:0] b = 8'd42;
add add_i(.*);
end
endgenerate
endmodule
EOT
# Missing wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
add add_i(.*);
endmodule
EOT
) 2>&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Incorrectly sized wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
wire [6:0] b = 6'd42;
add add_i(.*);
endmodule
EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Defaults
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
add add_i(.*);
endmodule
EOT
# Parameterised module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
add #(.N(8)) add_i(.*);
endmodule
EOT
# Parameterised blackbox module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
module top(input [7:0] a, b, output [7:0] q);
add #(.N(8)) add_i(.*);
endmodule
EOT
# Parameterised blackbox module - incorrect width
((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
module top(input [7:0] a, b, output [7:0] q);
add #(.N(6)) add_i(.*);
endmodule
EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
# Mixed implicit and explicit 1
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
add add_i(.b(8'd42), .*);
endmodule
EOT
# Mixed implicit and explicit 2
(../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, input [9:0] b, output [7:0] q);
add add_i(.b, .*);
endmodule
EOT
) 2>&1 | grep -F "Warning: Resizing cell port top.add_i.b from 10 bits to 8 bits." > /dev/null